[U-Boot] [PATCH 1/2] at91: modified NAND flash timing on meesc board

[Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>]

Hi Albert,

Albert ARIBAUD wrote:
> Hi Daniel,
> 
> Le 25/01/2012 14:19, Daniel Gorsulowski a ?crit :
>> Signed-off-by: Daniel Gorsulowski<Daniel.Gorsulowski@esd.eu>
>> ---
>>   board/esd/meesc/meesc.c |    8 ++++----
>>   1 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
>> index 4882ffc..9dd4375 100644
>> --- a/board/esd/meesc/meesc.c
>> +++ b/board/esd/meesc/meesc.c
>> @@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void)
>>       writel(csa,&matrix->csa[0]);
>>
>>       /* Configure SMC CS3 for NAND/SmartMedia */
>> -    writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
>> -        AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
>> +    writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
>> +        AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
>>           &smc->cs[3].setup);
>>
>>       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
>>           AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
>>           &smc->cs[3].pulse);
>>
>> -    writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
>> +    writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
>>           &smc->cs[3].cycle);
>>       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
>>           AT91_SMC_MODE_EXNW_DISABLE |
>>           AT91_SMC_MODE_DBW_8 |
>> -        AT91_SMC_MODE_TDF_CYCLE(3),
>> +        AT91_SMC_MODE_TDF_CYCLE(12),
>>           &smc->cs[3].mode);
>>
>>       /* Configure RDY/BSY */
> 
> Is this (and its counterpart for otc570) a performance improvement or a
> bug fix?.

There were problems with a new batch of NAND flashes in our production
process. We figured out, that the NAND timing is too fast.
So I would call this a bug fix.
> 
> Amicalement,
> --
> Albert.

Kind regards,
Daniel Gorsulowski