From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-1?Q?Christian_K=F6nig?= Subject: Re: [PATCH 2/4] drm/radeon/kms: no need to align IB like this Date: Thu, 23 Feb 2012 19:19:00 +0100 Message-ID: <4F468314.7030400@vodafone.de> References: <1330006725-2373-1-git-send-email-deathsimple@vodafone.de> <1330006725-2373-2-git-send-email-deathsimple@vodafone.de> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0119385581==" Return-path: Received: from outgoing.email.vodafone.de (outgoing.email.vodafone.de [139.7.28.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F7639EEA9 for ; Thu, 23 Feb 2012 10:19:04 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Jerome Glisse Cc: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org This is a multi-part message in MIME format. --===============0119385581== Content-Type: multipart/alternative; boundary="------------010105080304050006060400" This is a multi-part message in MIME format. --------------010105080304050006060400 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable On 23.02.2012 18:00, Jerome Glisse wrote: > > 2012/2/23 Christian K=F6nig > > > So don't confuse devs by doing so. > > Signed-off-by: Christian K=F6nig > > --- > drivers/gpu/drm/radeon/r600.c | 15 +-------------- > 1 files changed, 1 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/r600.c > b/drivers/gpu/drm/radeon/r600.c > index 4f08e5e..4a4ac8f 100644 > --- a/drivers/gpu/drm/radeon/r600.c > +++ b/drivers/gpu/drm/radeon/r600.c > @@ -2719,20 +2719,7 @@ int r600_ib_test(struct radeon_device > *rdev, int ring) > ib->ptr[0] =3D PACKET3(PACKET3_SET_CONFIG_REG, 1); > ib->ptr[1] =3D ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >>= 2); > ib->ptr[2] =3D 0xDEADBEEF; > - ib->ptr[3] =3D PACKET2(0); > - ib->ptr[4] =3D PACKET2(0); > - ib->ptr[5] =3D PACKET2(0); > - ib->ptr[6] =3D PACKET2(0); > - ib->ptr[7] =3D PACKET2(0); > - ib->ptr[8] =3D PACKET2(0); > - ib->ptr[9] =3D PACKET2(0); > - ib->ptr[10] =3D PACKET2(0); > - ib->ptr[11] =3D PACKET2(0); > - ib->ptr[12] =3D PACKET2(0); > - ib->ptr[13] =3D PACKET2(0); > - ib->ptr[14] =3D PACKET2(0); > - ib->ptr[15] =3D PACKET2(0); > - ib->length_dw =3D 16; > + ib->length_dw =3D 3; > r =3D radeon_ib_schedule(rdev, ib); > if (r) { > radeon_scratch_free(rdev, scratch); > -- > 1.7.5.4 > > > You sure about that ? I remember this helped with GPU lockup and i=20 > also seen fglrx aligning IB. Yeah, pretty much. Well I searched for halve an hour for the=20 corresponding IB alignment in mesa/the CS ioctl until I finally figured=20 out that there isn't any. So IBs submitted by usermode aren't aligned in any way.... So it really=20 seems to work fine and I couldn't find any reason why we should align an=20 IB for the GFX ring in our docs also. Christian. --------------010105080304050006060400 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit On 23.02.2012 18:00, Jerome Glisse wrote:

2012/2/23 Christian König <deathsimple@vodafone.de>
So don't confuse devs by doing so.

Signed-off-by: Christian König <deathsimple@vodafone.de>
---
 drivers/gpu/drm/radeon/r600.c |   15 +--------------
 1 files changed, 1 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 4f08e5e..4a4ac8f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2719,20 +2719,7 @@ int r600_ib_test(struct radeon_device *rdev, int ring)
       ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
       ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
       ib->ptr[2] = 0xDEADBEEF;
-       ib->ptr[3] = PACKET2(0);
-       ib->ptr[4] = PACKET2(0);
-       ib->ptr[5] = PACKET2(0);
-       ib->ptr[6] = PACKET2(0);
-       ib->ptr[7] = PACKET2(0);
-       ib->ptr[8] = PACKET2(0);
-       ib->ptr[9] = PACKET2(0);
-       ib->ptr[10] = PACKET2(0);
-       ib->ptr[11] = PACKET2(0);
-       ib->ptr[12] = PACKET2(0);
-       ib->ptr[13] = PACKET2(0);
-       ib->ptr[14] = PACKET2(0);
-       ib->ptr[15] = PACKET2(0);
-       ib->length_dw = 16;
+       ib->length_dw = 3;
       r = radeon_ib_schedule(rdev, ib);
       if (r) {
               radeon_scratch_free(rdev, scratch);
--
1.7.5.4

You sure about that ? I remember this helped with GPU lockup and i also seen fglrx aligning IB.
Yeah, pretty much. Well I searched for halve an hour for the corresponding IB alignment in mesa/the CS ioctl until I finally figured out that there isn't any.

So IBs submitted by usermode aren't aligned in any way.... So it really seems to work fine and I couldn't find any reason why we should align an IB for the GFX ring in our docs also.

Christian.
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