From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michael Lawnick Subject: Re: [PATCH 2/2] i2c/designware: Provide optional i2c bus recovery function Date: Thu, 01 Mar 2012 14:45:49 +0100 Message-ID: <4F4F7D8D.5040107@gmx.de> References: <0ca1d8990c23a45193a32d0e7e889620b995af59.1330082915.git.viresh.kumar@st.com> <351031347b845920a0ea78e7491d955137e3d7aa.1330082915.git.viresh.kumar@st.com> <4F4B3072.6050903@nvidia.com> <4F4B569F.3080607@st.com> <4F4B5A9A.4050303@st.com>, <4E01B0DA4B09044DB320A047A7063F8DCA93DAA13E@SAFEX1MAIL4.st.com> <4F4DB073.9030906@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4F4DB073.9030906-qxv4g6HH51o@public.gmane.org> Sender: linux-i2c-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Viresh Kumar Cc: Salvatore DE DOMINICIS , "khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org" , "ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org" , "w.sang-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org" , viresh kumar , Rajeev KUMAR , Shubhrajyoti Datta , Laxman Dewangan , Armando VISCONTI , Shiraz HASHIM , Vipin KUMAR , Deepak SIKRI , Vipul Kumar SAMAR , Amit VIRDI , Pratyush ANAND , Bhupesh SHARMA , Bhavna YADAV , Vincenzo FRASCINO , Mirko GARDI , "linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Giuseppe BARBA List-Id: linux-i2c@vger.kernel.org Am 29.02.2012 05:58, schrieb Viresh Kumar: ... > It says that the hang situation is "SDA is stuck LOW" and 9 clock pulses should > be enough to get it out of hang (Can somebody tell me how this figure of "9" > derived?) After 8 data bits there is direction change and ACK/NACK sent. AFAICS the number of clocks needed: The situation only occurs if slave was in read mode and drives a data-0. It will (only) see a NACK when it has driven the rest of current bits, fall back to idle and remaining cycles will be ignored. If master stops on first data-1 of slave, slave might ignore changes on SDA (iow start/stop flags) as it is still in read mode, i.e. driving actively data and not listening to SDA. > > SDA will become High, but what guarantees that this will not be low immediately > after that, while we are reading SDA line? Or Is reading SDA line after 9 pulses > sufficient? ... SDA may not go low while clock is high. This would be a violation of protocol. Except start/stop flag of master SDA transitions are always done while clock is low. HTH -- Michael