From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41053) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S87Qd-0000ek-Rs for qemu-devel@nongnu.org; Thu, 15 Mar 2012 05:57:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S87QD-0007PQ-1b for qemu-devel@nongnu.org; Thu, 15 Mar 2012 05:57:03 -0400 Received: from mx1.redhat.com ([209.132.183.28]:10768) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S87QC-0007PA-PX for qemu-devel@nongnu.org; Thu, 15 Mar 2012 05:56:36 -0400 Message-ID: <4F61BCC3.6020208@redhat.com> Date: Thu, 15 Mar 2012 10:56:19 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <1331802150-12183-1-git-send-email-dmitry.fleytman@ravellosystems.com> <1331802150-12183-4-git-send-email-dmitry.fleytman@ravellosystems.com> In-Reply-To: <1331802150-12183-4-git-send-email-dmitry.fleytman@ravellosystems.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/5] Header with various utility functions shared by VMWARE SCSI and network devices List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Dmitry Fleytman Cc: Anthony Liguori , Alex Fishman , "Michael S. Tsirkin" , yvugenfi@redhat.com, Izik Eidus , qemu-devel@nongnu.org, Yan Vugenfirer , Dmitry Fleytman Il 15/03/2012 10:02, Dmitry Fleytman ha scritto: > Signed-off-by: Dmitry Fleytman > Signed-off-by: Yan Vugenfirer > --- > hw/vmware_utils.h | 122 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 122 insertions(+), 0 deletions(-) > create mode 100644 hw/vmware_utils.h > > diff --git a/hw/vmware_utils.h b/hw/vmware_utils.h > new file mode 100644 > index 0000000..a86e691 > --- /dev/null > +++ b/hw/vmware_utils.h > @@ -0,0 +1,122 @@ > +/* > + * QEMU VMWARE paravirtual devices - auxiliary code > + * > + * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) > + * > + * Developed by Daynix Computing LTD (http://www.daynix.com) > + * > + * Authors: > + * Dmitry Fleytman > + * Yan Vugenfirer > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or later. > + * See the COPYING file in the top-level directory. > + * > + */ > + > +#ifndef VMWARE_UTILS_H > +#define VMWARE_UTILS_H > + > +/* Shared memory access functions with byte swap support */ > +static inline void > +vmw_shmem_read(target_phys_addr_t addr, void *buf, int len) > +{ > + DSHPRINTF("SHMEM r: %" PRIx64 ", len: %d to %p", addr, len, buf); Please add an #ifndef DSHPRINTF that defines it to nothing. > + cpu_physical_memory_read(addr, buf, len); > +} > + > +static inline void > +vmw_shmem_write(target_phys_addr_t addr, void *buf, int len) > +{ > + DSHPRINTF("SHMEM w: %" PRIx64 ", len: %d to %p", addr, len, buf); > + cpu_physical_memory_write(addr, buf, len); > +} > + > +static inline void > +vmw_shmem_rw(target_phys_addr_t addr, void *buf, int len, int is_write) > +{ > + DSHPRINTF("SHMEM r/w: %" PRIx64 ", len: %d (to %p), is write: %d", > + addr, len, buf, is_write); > + > + cpu_physical_memory_rw(addr, buf, len, is_write); > +} > + > +static inline void > +vmw_shmem_set(target_phys_addr_t addr, uint8 val, int len) > +{ > + int i; > + DSHPRINTF("SHMEM set: %" PRIx64 ", len: %d (value 0x%X)", addr, len, val); > + > + for (i = 0; i < len; i++) { > + cpu_physical_memory_write(addr + i, &val, 1); > + } > +} > + > +static inline uint32_t > +vmw_shmem_ld8(target_phys_addr_t addr) > +{ > + uint8_t res = ldub_phys(addr); > + DSHPRINTF("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res); > + return res; > +} > + > +static inline void > +vmw_shmem_st8(target_phys_addr_t addr, uint8_t value) > +{ > + DSHPRINTF("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value); > + stb_phys(addr, value); > +} > + > +static inline uint32_t > +vmw_shmem_ld16(target_phys_addr_t addr) > +{ > + uint16_t res = lduw_le_phys(addr); > + DSHPRINTF("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res); > + return res; > +} > + > +static inline void > +vmw_shmem_st16(target_phys_addr_t addr, uint16_t value) > +{ > + DSHPRINTF("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value); > + stw_le_phys(addr, value); > +} > + > +static inline uint32_t > +vmw_shmem_ld32(target_phys_addr_t addr) > +{ > + uint32_t res = ldl_le_phys(addr); > + DSHPRINTF("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res); > + return res; > +} > + > +static inline void > +vmw_shmem_st32(target_phys_addr_t addr, uint32_t value) > +{ > + DSHPRINTF("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value); > + stl_le_phys(addr, value); > +} > + > +static inline uint64_t > +vmw_shmem_ld64(target_phys_addr_t addr) > +{ > + uint64_t res = ldq_le_phys(addr); > + DSHPRINTF("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res); > + return res; > +} > + > +static inline void > +vmw_shmem_st64(target_phys_addr_t addr, uint64_t value) > +{ > + DSHPRINTF("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value); > + stq_le_phys(addr, value); > +} > + > +/* MACROS for simplification of operations on array-style registers */ > +#define IS_MULTIREG_ADDR(addr, base, cnt, regsize) \ > + (((addr) >= (base)) && ((addr) < (base) + (cnt) * (regsize))) > + > +#define MULTIREG_IDX_BY_ADDR(addr, base, regsize) \ > + (((addr) - (base)) / (regsize)) > + > +#endif Otherwise looks good. Paolo