From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45417) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SAUeW-0004AF-Fo for qemu-devel@nongnu.org; Wed, 21 Mar 2012 19:09:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SAUeU-0003Kf-BQ for qemu-devel@nongnu.org; Wed, 21 Mar 2012 19:09:12 -0400 Received: from usrksweb02.endace.com ([174.143.168.194]:46593) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SAUeU-0003KR-4L for qemu-devel@nongnu.org; Wed, 21 Mar 2012 19:09:10 -0400 Message-ID: <4F6A5F88.4070100@endace.com> Date: Thu, 22 Mar 2012 12:08:56 +1300 From: Alexey Korolev MIME-Version: 1.0 References: <1330479314.29508.7.camel@nzhmlwks0057.ad.endace.com> <20120321125858.GA21467@redhat.com> In-Reply-To: <20120321125858.GA21467@redhat.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] Fix typo in i400FX chipset init code List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: "qemu-devel@nongnu.org" > On Wed, Feb 29, 2012 at 02:35:14PM +1300, Alexey Korolev wrote: > I've fixed the commit message and applied. Thank you! > How does one trigger the problem? > I'd like to know so I can test for it. The i440fx_init() function is called from pc_init code. The call looks like that: pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, system_memory, system_io, ram_size, below_4g_mem_size, 0x100000000ULL - below_4g_mem_size, 0x100000000ULL + above_4g_mem_size, (sizeof(target_phys_addr_t) == 4 ? 0 : ((uint64_t)1 << 62)), pci_memory, ram_memory); So we have pci_hole64_size = 1 << 62 and because of typo we also have pci_hole64_start = 1 << 62 The pci_hole64_start & pci_hole64_size are used to build memory regions access ranges. Since 64bit PCI regions must be below 1<<40 and pci_hole64_start is 1 << 62, we have situations when all 64bit PCI regions are inaccessible. For how to test it: Convert device to use 64bit PCI BARs (ivshmem.c for example). Apply patches for 64 bit support in seabios: http://lists.nongnu.org/archive/html/qemu-devel/2012-03/msg00018.html. Try to access the content of 64bit PCI memory. It will fail! P/s: IMHO it makes sence to update pc_iix.c code as well. The pci_hole64_size value is incorrect anyway. >> --- >> >> hw/piix_pci.c | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/hw/piix_pci.c b/hw/piix_pci.c >> index 3ed3d90..aab8188 100644 >> --- a/hw/piix_pci.c >> +++ b/hw/piix_pci.c >> @@ -353,7 +353,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, >> b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic, >> address_space_mem, address_space_io, ram_size, >> pci_hole_start, pci_hole_size, >> - pci_hole64_size, pci_hole64_size, >> + pci_hole64_start, pci_hole64_size, >> pci_memory, ram_memory); >> return b; >> } >> >> >> >>