From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [Qemu-devel] [PATCH v4 5/7] RTC:Add RTC update-ended interrupt support Date: Thu, 22 Mar 2012 11:32:27 +0100 Message-ID: <4F6AFFBB.5000006@redhat.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: "Zhang, Yang Z" , "qemu-devel@nongnu.org" , "aliguori@us.ibm.com" , "kvm@vger.kernel.org" To: Stefano Stabellini Return-path: Received: from mx1.redhat.com ([209.132.183.28]:33116 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755712Ab2CVKcg (ORCPT ); Thu, 22 Mar 2012 06:32:36 -0400 In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: Il 22/03/2012 11:29, Stefano Stabellini ha scritto: >> The purpose of using two timer is trying to keep the UF, AF and UIP >> synchronous. User can poll UIP to check UF and AF bit. If we use >> timer for UF/AF bit track and check UIP by another way, since the >> timer will be fired with delay, then the problem is encountered: >> the UIP is cleared, but due to the delay of timer, the UF/AF bit is >> not set. So we need to check them on a same level. Although we can >> update UF/AF when reading it, the logic is too complicated, >> especially for AF bit. FWIW, the solution I used when I removed the second timer from the current code (not yet posted, I do hope your patches can be fixed!) was to set UIP when reading A, and clear it in the timer. You have something like that, but keep the two timers. Paolo From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52888) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SAfJx-00059s-29 for qemu-devel@nongnu.org; Thu, 22 Mar 2012 06:32:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SAfJq-0003ky-Sz for qemu-devel@nongnu.org; Thu, 22 Mar 2012 06:32:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:15960) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SAfJq-0003kj-KW for qemu-devel@nongnu.org; Thu, 22 Mar 2012 06:32:34 -0400 Message-ID: <4F6AFFBB.5000006@redhat.com> Date: Thu, 22 Mar 2012 11:32:27 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 5/7] RTC:Add RTC update-ended interrupt support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefano Stabellini Cc: "Zhang, Yang Z" , "aliguori@us.ibm.com" , "qemu-devel@nongnu.org" , "kvm@vger.kernel.org" Il 22/03/2012 11:29, Stefano Stabellini ha scritto: >> The purpose of using two timer is trying to keep the UF, AF and UIP >> synchronous. User can poll UIP to check UF and AF bit. If we use >> timer for UF/AF bit track and check UIP by another way, since the >> timer will be fired with delay, then the problem is encountered: >> the UIP is cleared, but due to the delay of timer, the UF/AF bit is >> not set. So we need to check them on a same level. Although we can >> update UF/AF when reading it, the logic is too complicated, >> especially for AF bit. FWIW, the solution I used when I removed the second timer from the current code (not yet posted, I do hope your patches can be fixed!) was to set UIP when reading A, and clear it in the timer. You have something like that, but keep the two timers. Paolo