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Date: Wed, 28 Mar 2012 18:47:21 +0200
From: =?ISO-8859-1?Q?Andreas_F=E4rber?= <afaerber@suse.de>
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/2] PPC: Fix TLB invalidation
 bug within the PPC interrupt handler.
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To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

Am 28.03.2012 02:45, schrieb David Gibson:
> On Tue, Mar 27, 2012 at 04:41:55PM +0100, Mark Cave-Ayland wrote:
>> Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subt=
le TLB
>> flush bug. By applying a mask to the interrupt MSR which cleared the I=
R/DR
>> bits at the start of the interrupt handler, the logic towards the end =
of the
>> handler to force a TLB flush if either one of these bits were set woul=
d never
>> be triggered.
>>
>> This patch simply changes the IR/DR bit check in the TLB flush logic t=
o use
>> the original MSR value (albeit with some interrupt-specific bits clear=
ed) so
>> that the IR/DR bits are preserved at the point where the check takes p=
lace.
>>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>=20
> Acked-by: David Gibson <david@gibson.dropbear.id.au>

Thanks, compile-tested and applied to ppc-next:
http://repo.or.cz/w/qemu/agraf.git/shortlog/refs/heads/ppc-next

Andreas

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