From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDL9s-0001ZY-NN for qemu-devel@nongnu.org; Thu, 29 Mar 2012 15:37:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDL9q-0005xP-SB for qemu-devel@nongnu.org; Thu, 29 Mar 2012 15:37:20 -0400 Message-ID: <4F74B2C9.4020202@freescale.com> Date: Thu, 29 Mar 2012 14:06:49 -0500 From: Scott Wood MIME-Version: 1.0 References: <1332862915-27501-1-git-send-email-mark.cave-ayland@ilande.co.uk> <1332862915-27501-2-git-send-email-mark.cave-ayland@ilande.co.uk> <4F71FD34.2040200@freescale.com> <20120328004653.GE9582@truffala.fritz.box> <4F742739.30008@ilande.co.uk> In-Reply-To: <4F742739.30008@ilande.co.uk> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Cave-Ayland Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 03/29/2012 04:11 AM, Mark Cave-Ayland wrote: >>> What about POWERPC_EXCP_40x? And are all the classic chips OK with the >>> 2.06B implementation? >> >> Hrm, yeah. I think what you ought to do is to use the new logic just >> for the "classic" exception models. Have the default branch remain >> the one that just masks ME. That's wrong, but it's the same wrong as >> we have already, and we can fix it later once we've verified what the >> right thing to do is for 40x and BookE. > > I'm actually coming at this from a fixing what was potentially an > OpenBIOS bug rather than a PPC angle, so I have to admit I have no I > idea which ones are the "classic" exception models. Would you consider > this to be just EXCP_STD, EXCP_6* and EXCP_7*? Also POWERPC_EXCP_G2, and maybe POWERPC_EXCP_970? Even on server there's a question of whether it's a 2.06 chip or previous version of the architecture. One thing that sticks out for classic chips that is missing here is MSR[POW], which should be cleared on exceptions. -Scott