Re: [Qemu-devel] [PATCH 02/13] hw/arm_gic: Move gic_get_current_cpu into arm_gic.c

[Evgeny Voevodin <e.voevodin@samsung.com>]

On 04.04.2012 19:30, Peter Maydell wrote:
> Move the gic_get_current_cpu() function into arm_gic.c.
> There are only two implementations: (1) "get the index
> of the currently executing CPU", used by all multicore
> GICs, and (2) "always 0", used by all GICs instantiated
> with a single CPU interface (the Realview board GIC and
> the v7M NVIC). So we can move this into the main GIC
> source file.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   hw/a15mpcore.c      |    8 --------
>   hw/a9mpcore.c       |    9 ---------
>   hw/arm11mpcore.c    |    6 ------
>   hw/arm_gic.c        |   20 +++++++++++++++-----
>   hw/armv7m_nvic.c    |    7 -------
>   hw/exynos4210_gic.c |    6 ------
>   hw/realview_gic.c   |    7 -------
>   7 files changed, 15 insertions(+), 48 deletions(-)
>
> diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c
> index 67206ec..2e2ed42 100644
> --- a/hw/a15mpcore.c
> +++ b/hw/a15mpcore.c
> @@ -20,14 +20,6 @@
>
>   #include "sysbus.h"
>
> -/* Configuration for arm_gic.c:
> - * how to ID current CPU
> - */
> -static inline int gic_get_current_cpu(void)
> -{
> -  return cpu_single_env->cpu_index;
> -}
> -
>   #include "arm_gic.c"
>
>   /* A15MP private memory region.  */
> diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
> index 5bbe3c7..1d83c37 100644
> --- a/hw/a9mpcore.c
> +++ b/hw/a9mpcore.c
> @@ -10,15 +10,6 @@
>
>   #include "sysbus.h"
>
> -/* Configuration for arm_gic.c:
> - * how to ID current CPU
> - */
> -static inline int
> -gic_get_current_cpu(void)
> -{
> -  return cpu_single_env->cpu_index;
> -}
> -
>   #include "arm_gic.c"
>
>   /* A9MP private memory region.  */
> diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
> index 99c1826..c4829d8 100644
> --- a/hw/arm11mpcore.c
> +++ b/hw/arm11mpcore.c
> @@ -10,12 +10,6 @@
>   #include "sysbus.h"
>   #include "qemu-timer.h"
>
> -static inline int
> -gic_get_current_cpu(void)
> -{
> -  return cpu_single_env->cpu_index;
> -}
> -
>   #include "arm_gic.c"
>
>   /* MPCore private memory region.  */
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index f64a001..df1a34b 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -126,6 +126,16 @@ typedef struct gic_state
>       uint32_t num_irq;
>   } gic_state;
>
> +static inline int gic_get_current_cpu(gic_state *s)
> +{
> +#if NCPU>  1
> +    if (s->num_cpu>  1) {
> +        return cpu_single_env->cpu_index;
> +    }
> +#endif
> +    return 0;
> +}
> +
>   /* TODO: Many places that call this routine could be optimized.  */
>   /* Update interrupt status after enabled or pending bits have been changed.  */
>   static void gic_update(gic_state *s)
> @@ -285,7 +295,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
>       int cm;
>       int mask;
>
> -    cpu = gic_get_current_cpu();
> +    cpu = gic_get_current_cpu(s);
>       cm = 1<<  cpu;
>       if (offset<  0x100) {
>   #ifndef NVIC
> @@ -420,7 +430,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
>       int i;
>       int cpu;
>
> -    cpu = gic_get_current_cpu();
> +    cpu = gic_get_current_cpu(s);
>       if (offset<  0x100) {
>   #ifdef NVIC
>           goto bad_reg;
> @@ -582,7 +592,7 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
>           int irq;
>           int mask;
>
> -        cpu = gic_get_current_cpu();
> +        cpu = gic_get_current_cpu(s);
>           irq = value&  0x3ff;
>           switch ((value>>  24)&  3) {
>           case 0:
> @@ -665,14 +675,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
>                                    unsigned size)
>   {
>       gic_state *s = (gic_state *)opaque;
> -    return gic_cpu_read(s, gic_get_current_cpu(), addr);
> +    return gic_cpu_read(s, gic_get_current_cpu(s), addr);
>   }
>
>   static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
>                                 uint64_t value, unsigned size)
>   {
>       gic_state *s = (gic_state *)opaque;
> -    gic_cpu_write(s, gic_get_current_cpu(), addr, value);
> +    gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
>   }
>
>   /* Wrappers to read/write the GIC CPU interface for a specific CPU.
> diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
> index bdab709..99ed85b 100644
> --- a/hw/armv7m_nvic.c
> +++ b/hw/armv7m_nvic.c
> @@ -17,13 +17,6 @@
>
>   #define NVIC 1
>
> -/* Only a single "CPU" interface is present.  */
> -static inline int
> -gic_get_current_cpu(void)
> -{
> -    return 0;
> -}
> -
>   static uint32_t nvic_readl(void *opaque, uint32_t offset);
>   static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
>
> diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c
> index 426f540..ff7ab84 100644
> --- a/hw/exynos4210_gic.c
> +++ b/hw/exynos4210_gic.c
> @@ -262,12 +262,6 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
>
>   /********* GIC part *********/
>
> -static inline int
> -gic_get_current_cpu(void)
> -{
> -    return cpu_single_env->cpu_index;
> -}
> -
>   #include "arm_gic.c"
>
>   typedef struct {
> diff --git a/hw/realview_gic.c b/hw/realview_gic.c
> index d114242..aa780fe 100644
> --- a/hw/realview_gic.c
> +++ b/hw/realview_gic.c
> @@ -9,13 +9,6 @@
>
>   #include "sysbus.h"
>
> -/* Only a single "CPU" interface is present.  */
> -static inline int
> -gic_get_current_cpu(void)
> -{
> -  return 0;
> -}
> -
>   #include "arm_gic.c"
>
>   typedef struct {

Reviewed-by: Evgeny Voevodin<e.voevodin@samsung.com>


-- 
Kind regards,
Evgeny Voevodin,
Leading Software Engineer,
ASWG, Moscow R&D center, Samsung Electronics
e-mail: e.voevodin@samsung.com