From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from [222.73.24.84] (helo=song.cn.fujitsu.com) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SHmis-0001jQ-BR for kexec@lists.infradead.org; Wed, 11 Apr 2012 01:51:51 +0000 Message-ID: <4F84E365.10201@cn.fujitsu.com> Date: Wed, 11 Apr 2012 09:50:29 +0800 From: zhangyanfei MIME-Version: 1.0 Subject: [PATCH 2/4] KVM: VMX: Add functions to fill VMCSINFO References: <4F84E0DF.8040206@cn.fujitsu.com> In-Reply-To: <4F84E0DF.8040206@cn.fujitsu.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: kexec-bounces@lists.infradead.org Errors-To: kexec-bounces+dwmw2=infradead.org@lists.infradead.org To: avi@redhat.com, mtosatti@redhat.com Cc: dzickus@redhat.com, luto@mit.edu, kvm@vger.kernel.org, joerg.roedel@amd.com, gregkh@suse.de, kexec@lists.infradead.org, linux-kernel@vger.kernel.org, paul.gortmaker@windriver.com, ludwig.nussel@suse.de, ebiederm@xmission.com VGhpcyBwYXRjaCBpcyB0byBpbXBsZW1lbnQgdGhlIGZlYXR1cmUgdGhhdCBhdCBpbml0aWFsaXph dGlvbiBvZgprdm1faW50ZWwgbW9kdWxlLCBmaWxscyBWTUNTSU5GTyB3aXRoIGEgVk1DUyByZXZp c2lvbiBpZGVudGlmaWVyLAphbmQgZW5jb2RlZCBvZmZzZXRzIG9mIFZNQ1MgZmllbGRzLiBUaGUg cmVhc29uIHdoeSB3ZSBwdXQgdGhlClZNQ1NJTkZPIHByb2Nlc3NpbmcgYXQgdGhlIGluaXRpYWxp emF0aW9uIG9mIGt2bV9pbnRlbCBtb2R1bGUKaXMgdGhhdCBpdCdzIGRhbmdlcm91cyB0byByb2Ig Vk1YIHJlc291cmNlcyB3aGlsZSBrdm0gbW9kdWxlIGlzCmxvYWRlZC4KCk5vdGUsIG9mZnNldHMg b2YgZmllbGRzIGJlbG93IHdpbGwgbm90IGJlIGZpbGxlZCBpbnRvIFZNQ1NJTkZPOgoxLiBmaWVs ZHMgZGVmaW5lZCBpbiBJbnRlbCBzcGVjaWZpY2F0aW9uIChJbnRlbMKuIDY0IGFuZAogICBJQS0z MiBBcmNoaXRlY3R1cmVzIFNvZnR3YXJlIERldmVsb3BlcuKAmXMgTWFudWFsLCBWb2x1bWUKICAg M0MpIGJ1dCBub3QgZGVmaW5lZCBpbiAqdm1jc19maWVsZCouCjIuIGZpZWxkcyBkb24ndCBleGlz dCBiZWNhdXNlIHRoZWlyIGNvcnJlc3BvbmRpbmcgY29udHJvbCBiaXRzCiAgIGFyZSBub3Qgc2V0 LgoKU2lnbmVkLW9mZi1ieTogemhhbmd5YW5mZWkgPHpoYW5neWFuZmVpQGNuLmZ1aml0c3UuY29t PgotLS0KIGFyY2gveDg2L2t2bS92bXguYyB8ICAzNTAgKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrKwogMSBmaWxlcyBjaGFuZ2VkLCAzNTAgaW5zZXJ0 aW9ucygrKSwgMCBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9rdm0vdm14LmMg Yi9hcmNoL3g4Ni9rdm0vdm14LmMKaW5kZXggYWQ4NWFkZi4uZTk4ZmFmYSAxMDA2NDQKLS0tIGEv YXJjaC94ODYva3ZtL3ZteC5jCisrKyBiL2FyY2gveDg2L2t2bS92bXguYwpAQCAtNDEsNiArNDEs NyBAQAogI2luY2x1ZGUgPGFzbS9pMzg3Lmg+CiAjaW5jbHVkZSA8YXNtL3hjci5oPgogI2luY2x1 ZGUgPGFzbS9wZXJmX2V2ZW50Lmg+CisjaW5jbHVkZSA8YXNtL3ZtY3NpbmZvLmg+CiAKICNpbmNs dWRlICJ0cmFjZS5oIgogCkBAIC0yNTk5LDYgKzI2MDAsMzUzIEBAIHN0YXRpYyBfX2luaXQgaW50 IGFsbG9jX2t2bV9hcmVhKHZvaWQpCiAJcmV0dXJuIDA7CiB9CiAKKy8qCisgKiBGb3IgY2FjdWxh dGluZyBvZmZzZXRzIG9mIGZpZWxkcyBpbiBWTUNTIGRhdGEsIHdlIGluZGV4IGV2ZXJ5IDE2LWJp dAorICogZmllbGQgYnkgdGhpcyBraW5kIG9mIGZvcm1hdDoKKyAqICAgICAgICAgfCAtLS0tLS0t LS0gMTYgYml0cyAtLS0tLS0tLS0tIHwKKyAqICAgICAgICAgKy0tLS0tLS0tLS0tLS0rLSstLS0t LS0tLS0tLS0rLSsKKyAqICAgICAgICAgfCBoaWdoIDcgYml0cyB8MXwgbG93IDcgYml0cyB8MHwK KyAqICAgICAgICAgKy0tLS0tLS0tLS0tLS0rLSstLS0tLS0tLS0tLS0rLSsKKyAqIEluIGhpZ2gg Ynl0ZSwgdGhlIGxvd2VzdCBiaXQgbXVzdCBiZSAxOyBJbiBsb3cgYnl0ZSwgdGhlIGxvd2VzdCBi aXQKKyAqIG11c3QgYmUgMC4gVGhlIHR3byBiaXRzIGFyZSBzZXQgbGlrZSB0aGlzIGluIGNhc2Ug aW5kZXhlcyBpbiBWTUNTCisgKiBkYXRhIGFyZSByZWFkIGFzIGJpZyBlbmRpYW4gbW9kZS4KKyAq IFRoZSByZW1haW5pbmcgMTQgYml0cyBvZiB0aGUgaW5kZXggaW5kaWNhdGUgdGhlIHJlYWwgb2Zm c2V0IG9mIHRoZQorICogZmllbGQuIEJlY2F1c2UgdGhlIHNpemUgb2YgYSBWTUNTIHJlZ2lvbiBp cyBhdCBtb3N0IDQgS0J5dGVzLCBzbworICogMTQgYml0cyBhcmUgZW5vdWdoIHRvIGluZGV4IHRo ZSB3aG9sZSBWTUNTIHJlZ2lvbi4KKyAqCisgKiBFTkNPRElOR19PRkZTRVQ6IGVuY29kZSB0aGUg b2Zmc2V0IGludG8gdGhlIGluZGV4IG9mIHRoaXMga2luZC4KKyAqLworI2RlZmluZSBPRkZTRVRf SElHSF9TSElGVCAoNykKKyNkZWZpbmUgT0ZGU0VUX0xPV19NQVNLICAgKCgxIDw8IE9GRlNFVF9I SUdIX1NISUZUKSAtIDEpIC8qIDB4N2YgKi8KKyNkZWZpbmUgT0ZGU0VUX0hJR0hfTUFTSyAgKE9G RlNFVF9MT1dfTUFTSyA8PCBPRkZTRVRfSElHSF9TSElGVCkgLyogMHgzZjgwICovCisjZGVmaW5l IEVOQ09ESU5HX09GRlNFVChvZmZzZXQpIFwKKwkoKCgob2Zmc2V0KSAmIE9GRlNFVF9MT1dfTUFT SykgPDwgMSkgKyBcCisJKCgoKG9mZnNldCkgJiBPRkZTRVRfSElHSF9NQVNLKSA8PCAyKSB8IDB4 MTAwKSkKKworLyoKKyAqIFdlIHNlcGFyYXRlIHRoZXNlIGZpdmUgY29udHJvbCBmaWVsZHMgZnJv bSBvdGhlciBmaWVsZHMKKyAqIGJlY2F1c2Ugc29tZSBmaWVsZHMgb25seSBleGlzdCBvbiBwcm9j ZXNzb3JzIHRoYXQgc3VwcG9ydAorICogdGhlIDEtc2V0dGluZyBvZiBjb250cm9sIGJpdHMgaW4g dGhlIGZpdmUgY29udHJvbCBmaWVsZHMuCisgKi8KK3N0YXRpYyBpbmxpbmUgdm9pZCBhcHBlbmRf Y29udHJvbF9maWVsZCh2b2lkKQoreworI2RlZmluZSBDT05UUk9MX0ZJRUxEX09GRlNFVChmaWVs ZCkgXAorCVZNQ1NJTkZPX0ZJRUxEMzIoZmllbGQsIHZtY3NfcmVhZDMyKGZpZWxkKSkKKworCUNP TlRST0xfRklFTERfT0ZGU0VUKFBJTl9CQVNFRF9WTV9FWEVDX0NPTlRST0wpOworCUNPTlRST0xf RklFTERfT0ZGU0VUKENQVV9CQVNFRF9WTV9FWEVDX0NPTlRST0wpOworCWlmIChjcHVfaGFzX3Nl Y29uZGFyeV9leGVjX2N0cmxzKCkpIHsKKwkJQ09OVFJPTF9GSUVMRF9PRkZTRVQoU0VDT05EQVJZ X1ZNX0VYRUNfQ09OVFJPTCk7CisJfQorCUNPTlRST0xfRklFTERfT0ZGU0VUKFZNX0VYSVRfQ09O VFJPTFMpOworCUNPTlRST0xfRklFTERfT0ZGU0VUKFZNX0VOVFJZX0NPTlRST0xTKTsKK30KKwor c3RhdGljIGlubGluZSB2b2lkIGFwcGVuZF9maWVsZDE2KHZvaWQpCit7CisjZGVmaW5lIEZJRUxE X09GRlNFVDE2KGZpZWxkKSBcCisJVk1DU0lORk9fRklFTEQxNihmaWVsZCwgdm1jc19yZWFkMTYo ZmllbGQpKTsKKworCUZJRUxEX09GRlNFVDE2KEdVRVNUX0VTX1NFTEVDVE9SKTsKKwlGSUVMRF9P RkZTRVQxNihHVUVTVF9DU19TRUxFQ1RPUik7CisJRklFTERfT0ZGU0VUMTYoR1VFU1RfU1NfU0VM RUNUT1IpOworCUZJRUxEX09GRlNFVDE2KEdVRVNUX0RTX1NFTEVDVE9SKTsKKwlGSUVMRF9PRkZT RVQxNihHVUVTVF9GU19TRUxFQ1RPUik7CisJRklFTERfT0ZGU0VUMTYoR1VFU1RfR1NfU0VMRUNU T1IpOworCUZJRUxEX09GRlNFVDE2KEdVRVNUX0xEVFJfU0VMRUNUT1IpOworCUZJRUxEX09GRlNF VDE2KEdVRVNUX1RSX1NFTEVDVE9SKTsKKwlGSUVMRF9PRkZTRVQxNihIT1NUX0VTX1NFTEVDVE9S KTsKKwlGSUVMRF9PRkZTRVQxNihIT1NUX0NTX1NFTEVDVE9SKTsKKwlGSUVMRF9PRkZTRVQxNihI T1NUX1NTX1NFTEVDVE9SKTsKKwlGSUVMRF9PRkZTRVQxNihIT1NUX0RTX1NFTEVDVE9SKTsKKwlG SUVMRF9PRkZTRVQxNihIT1NUX0ZTX1NFTEVDVE9SKTsKKwlGSUVMRF9PRkZTRVQxNihIT1NUX0dT X1NFTEVDVE9SKTsKKwlGSUVMRF9PRkZTRVQxNihIT1NUX1RSX1NFTEVDVE9SKTsKK30KKworc3Rh dGljIGlubGluZSB2b2lkIGFwcGVuZF9maWVsZDY0KHZvaWQpCit7CisjZGVmaW5lIEZJRUxEX09G RlNFVDY0KGZpZWxkKSBcCisJVk1DU0lORk9fRklFTEQ2NChmaWVsZCwgdm1jc19yZWFkNjQoZmll bGQpKTsKKworCUZJRUxEX09GRlNFVDY0KElPX0JJVE1BUF9BKTsKKwlGSUVMRF9PRkZTRVQ2NChJ T19CSVRNQVBfQV9ISUdIKTsKKwlGSUVMRF9PRkZTRVQ2NChJT19CSVRNQVBfQik7CisJRklFTERf T0ZGU0VUNjQoSU9fQklUTUFQX0JfSElHSCk7CisJRklFTERfT0ZGU0VUNjQoVk1fRVhJVF9NU1Jf U1RPUkVfQUREUik7CisJRklFTERfT0ZGU0VUNjQoVk1fRVhJVF9NU1JfU1RPUkVfQUREUl9ISUdI KTsKKwlGSUVMRF9PRkZTRVQ2NChWTV9FWElUX01TUl9MT0FEX0FERFIpOworCUZJRUxEX09GRlNF VDY0KFZNX0VYSVRfTVNSX0xPQURfQUREUl9ISUdIKTsKKwlGSUVMRF9PRkZTRVQ2NChWTV9FTlRS WV9NU1JfTE9BRF9BRERSKTsKKwlGSUVMRF9PRkZTRVQ2NChWTV9FTlRSWV9NU1JfTE9BRF9BRERS X0hJR0gpOworCUZJRUxEX09GRlNFVDY0KFRTQ19PRkZTRVQpOworCUZJRUxEX09GRlNFVDY0KFRT Q19PRkZTRVRfSElHSCk7CisJRklFTERfT0ZGU0VUNjQoVk1DU19MSU5LX1BPSU5URVIpOworCUZJ RUxEX09GRlNFVDY0KFZNQ1NfTElOS19QT0lOVEVSX0hJR0gpOworCUZJRUxEX09GRlNFVDY0KEdV RVNUX0lBMzJfREVCVUdDVEwpOworCUZJRUxEX09GRlNFVDY0KEdVRVNUX0lBMzJfREVCVUdDVExf SElHSCk7CisKKwlpZiAoY3B1X2hhc192bXhfbXNyX2JpdG1hcCgpKSB7CisJCUZJRUxEX09GRlNF VDY0KE1TUl9CSVRNQVApOworCQlGSUVMRF9PRkZTRVQ2NChNU1JfQklUTUFQX0hJR0gpOworCX0K KworCWlmIChjcHVfaGFzX3ZteF90cHJfc2hhZG93KCkpIHsKKwkJRklFTERfT0ZGU0VUNjQoVklS VFVBTF9BUElDX1BBR0VfQUREUik7CisJCUZJRUxEX09GRlNFVDY0KFZJUlRVQUxfQVBJQ19QQUdF X0FERFJfSElHSCk7CisJfQorCisJaWYgKGNwdV9oYXNfc2Vjb25kYXJ5X2V4ZWNfY3RybHMoKSkg eworCQlpZiAodm1jc19jb25maWcuY3B1X2Jhc2VkXzJuZF9leGVjX2N0cmwgJgorCQkgICAgU0VD T05EQVJZX0VYRUNfVklSVFVBTElaRV9BUElDX0FDQ0VTU0VTKSB7CisJCQlGSUVMRF9PRkZTRVQ2 NChBUElDX0FDQ0VTU19BRERSKTsKKwkJCUZJRUxEX09GRlNFVDY0KEFQSUNfQUNDRVNTX0FERFJf SElHSCk7CisJCX0KKwkJaWYgKGNwdV9oYXNfdm14X2VwdCgpKSB7CisJCQlGSUVMRF9PRkZTRVQ2 NChFUFRfUE9JTlRFUik7CisJCQlGSUVMRF9PRkZTRVQ2NChFUFRfUE9JTlRFUl9ISUdIKTsKKwkJ CUZJRUxEX09GRlNFVDY0KEdVRVNUX1BIWVNJQ0FMX0FERFJFU1MpOworCQkJRklFTERfT0ZGU0VU NjQoR1VFU1RfUEhZU0lDQUxfQUREUkVTU19ISUdIKTsKKwkJCUZJRUxEX09GRlNFVDY0KEdVRVNU X1BEUFRSMCk7CisJCQlGSUVMRF9PRkZTRVQ2NChHVUVTVF9QRFBUUjBfSElHSCk7CisJCQlGSUVM RF9PRkZTRVQ2NChHVUVTVF9QRFBUUjEpOworCQkJRklFTERfT0ZGU0VUNjQoR1VFU1RfUERQVFIx X0hJR0gpOworCQkJRklFTERfT0ZGU0VUNjQoR1VFU1RfUERQVFIyKTsKKwkJCUZJRUxEX09GRlNF VDY0KEdVRVNUX1BEUFRSMl9ISUdIKTsKKwkJCUZJRUxEX09GRlNFVDY0KEdVRVNUX1BEUFRSMyk7 CisJCQlGSUVMRF9PRkZTRVQ2NChHVUVTVF9QRFBUUjNfSElHSCk7CisJCX0KKwl9CisKKwlpZiAo dm1jc19jb25maWcudm1leGl0X2N0cmwgJiBWTV9FWElUX1NBVkVfSUEzMl9QQVQgfHwgXAorCSAg ICB2bWNzX2NvbmZpZy52bWVudHJ5X2N0cmwgJiBWTV9FTlRSWV9MT0FEX0lBMzJfUEFUKSB7CisJ CUZJRUxEX09GRlNFVDY0KEdVRVNUX0lBMzJfUEFUKTsKKwkJRklFTERfT0ZGU0VUNjQoR1VFU1Rf SUEzMl9QQVRfSElHSCk7CisJfQorCisJaWYgKHZtY3NfY29uZmlnLnZtZXhpdF9jdHJsICYgVk1f RVhJVF9TQVZFX0lBMzJfRUZFUiB8fCBcCisJICAgIHZtY3NfY29uZmlnLnZtZW50cnlfY3RybCAm IFZNX0VOVFJZX0xPQURfSUEzMl9FRkVSKSB7CisJCUZJRUxEX09GRlNFVDY0KEdVRVNUX0lBMzJf RUZFUik7CisJCUZJRUxEX09GRlNFVDY0KEdVRVNUX0lBMzJfRUZFUl9ISUdIKTsKKwl9CisKKwlp ZiAodm1jc19jb25maWcudm1lbnRyeV9jdHJsICYgVk1fRU5UUllfTE9BRF9JQTMyX1BFUkZfR0xP QkFMX0NUUkwpIHsKKwkJRklFTERfT0ZGU0VUNjQoR1VFU1RfSUEzMl9QRVJGX0dMT0JBTF9DVFJM KTsKKwkJRklFTERfT0ZGU0VUNjQoR1VFU1RfSUEzMl9QRVJGX0dMT0JBTF9DVFJMX0hJR0gpOwor CX0KKworCWlmICh2bWNzX2NvbmZpZy52bWV4aXRfY3RybCAmIFZNX0VYSVRfTE9BRF9JQTMyX1BB VCkgeworCQlGSUVMRF9PRkZTRVQ2NChIT1NUX0lBMzJfUEFUKTsKKwkJRklFTERfT0ZGU0VUNjQo SE9TVF9JQTMyX1BBVF9ISUdIKTsKKwl9CisKKwlpZiAodm1jc19jb25maWcudm1leGl0X2N0cmwg JiBWTV9FWElUX0xPQURfSUEzMl9FRkVSKSB7CisJCUZJRUxEX09GRlNFVDY0KEhPU1RfSUEzMl9F RkVSKTsKKwkJRklFTERfT0ZGU0VUNjQoSE9TVF9JQTMyX0VGRVJfSElHSCk7CisJfQorCisJaWYg KHZtY3NfY29uZmlnLnZtZXhpdF9jdHJsICYgVk1fRVhJVF9MT0FEX0lBMzJfUEVSRl9HTE9CQUxf Q1RSTCkgeworCQlGSUVMRF9PRkZTRVQ2NChIT1NUX0lBMzJfUEVSRl9HTE9CQUxfQ1RSTCk7CisJ CUZJRUxEX09GRlNFVDY0KEhPU1RfSUEzMl9QRVJGX0dMT0JBTF9DVFJMX0hJR0gpOworCX0KK30K Kworc3RhdGljIGlubGluZSB2b2lkIGFwcGVuZF9maWVsZDMyKHZvaWQpCit7CisjZGVmaW5lIEZJ RUxEX09GRlNFVDMyKGZpZWxkKSBcCisJVk1DU0lORk9fRklFTEQzMihmaWVsZCwgdm1jc19yZWFk MzIoZmllbGQpKTsKKworCUZJRUxEX09GRlNFVDMyKEVYQ0VQVElPTl9CSVRNQVApOworCUZJRUxE X09GRlNFVDMyKFBBR0VfRkFVTFRfRVJST1JfQ09ERV9NQVNLKTsKKwlGSUVMRF9PRkZTRVQzMihQ QUdFX0ZBVUxUX0VSUk9SX0NPREVfTUFUQ0gpOworCUZJRUxEX09GRlNFVDMyKENSM19UQVJHRVRf Q09VTlQpOworCUZJRUxEX09GRlNFVDMyKFZNX0VYSVRfTVNSX1NUT1JFX0NPVU5UKTsKKwlGSUVM RF9PRkZTRVQzMihWTV9FWElUX01TUl9MT0FEX0NPVU5UKTsKKwlGSUVMRF9PRkZTRVQzMihWTV9F TlRSWV9NU1JfTE9BRF9DT1VOVCk7CisJRklFTERfT0ZGU0VUMzIoVk1fRU5UUllfSU5UUl9JTkZP X0ZJRUxEKTsKKwlGSUVMRF9PRkZTRVQzMihWTV9FTlRSWV9FWENFUFRJT05fRVJST1JfQ09ERSk7 CisJRklFTERfT0ZGU0VUMzIoVk1fRU5UUllfSU5TVFJVQ1RJT05fTEVOKTsKKwlGSUVMRF9PRkZT RVQzMihWTV9JTlNUUlVDVElPTl9FUlJPUik7CisJRklFTERfT0ZGU0VUMzIoVk1fRVhJVF9SRUFT T04pOworCUZJRUxEX09GRlNFVDMyKFZNX0VYSVRfSU5UUl9JTkZPKTsKKwlGSUVMRF9PRkZTRVQz MihWTV9FWElUX0lOVFJfRVJST1JfQ09ERSk7CisJRklFTERfT0ZGU0VUMzIoSURUX1ZFQ1RPUklO R19JTkZPX0ZJRUxEKTsKKwlGSUVMRF9PRkZTRVQzMihJRFRfVkVDVE9SSU5HX0VSUk9SX0NPREUp OworCUZJRUxEX09GRlNFVDMyKFZNX0VYSVRfSU5TVFJVQ1RJT05fTEVOKTsKKwlGSUVMRF9PRkZT RVQzMihWTVhfSU5TVFJVQ1RJT05fSU5GTyk7CisJRklFTERfT0ZGU0VUMzIoR1VFU1RfRVNfTElN SVQpOworCUZJRUxEX09GRlNFVDMyKEdVRVNUX0NTX0xJTUlUKTsKKwlGSUVMRF9PRkZTRVQzMihH VUVTVF9TU19MSU1JVCk7CisJRklFTERfT0ZGU0VUMzIoR1VFU1RfRFNfTElNSVQpOworCUZJRUxE X09GRlNFVDMyKEdVRVNUX0ZTX0xJTUlUKTsKKwlGSUVMRF9PRkZTRVQzMihHVUVTVF9HU19MSU1J VCk7CisJRklFTERfT0ZGU0VUMzIoR1VFU1RfTERUUl9MSU1JVCk7CisJRklFTERfT0ZGU0VUMzIo R1VFU1RfVFJfTElNSVQpOworCUZJRUxEX09GRlNFVDMyKEdVRVNUX0dEVFJfTElNSVQpOworCUZJ RUxEX09GRlNFVDMyKEdVRVNUX0lEVFJfTElNSVQpOworCUZJRUxEX09GRlNFVDMyKEdVRVNUX0VT X0FSX0JZVEVTKTsKKwlGSUVMRF9PRkZTRVQzMihHVUVTVF9DU19BUl9CWVRFUyk7CisJRklFTERf T0ZGU0VUMzIoR1VFU1RfU1NfQVJfQllURVMpOworCUZJRUxEX09GRlNFVDMyKEdVRVNUX0RTX0FS X0JZVEVTKTsKKwlGSUVMRF9PRkZTRVQzMihHVUVTVF9GU19BUl9CWVRFUyk7CisJRklFTERfT0ZG U0VUMzIoR1VFU1RfR1NfQVJfQllURVMpOworCUZJRUxEX09GRlNFVDMyKEdVRVNUX0xEVFJfQVJf QllURVMpOworCUZJRUxEX09GRlNFVDMyKEdVRVNUX1RSX0FSX0JZVEVTKTsKKwlGSUVMRF9PRkZT RVQzMihHVUVTVF9JTlRFUlJVUFRJQklMSVRZX0lORk8pOworCUZJRUxEX09GRlNFVDMyKEdVRVNU X0FDVElWSVRZX1NUQVRFKTsKKwlGSUVMRF9PRkZTRVQzMihHVUVTVF9TWVNFTlRFUl9DUyk7CisJ RklFTERfT0ZGU0VUMzIoSE9TVF9JQTMyX1NZU0VOVEVSX0NTKTsKKworCWlmIChjcHVfaGFzX3Zt eF90cHJfc2hhZG93KCkpIHsKKwkJRklFTERfT0ZGU0VUMzIoVFBSX1RIUkVTSE9MRCk7CisJfQor CWlmIChjcHVfaGFzX3NlY29uZGFyeV9leGVjX2N0cmxzKCkpIHsKKwkJaWYgKGNwdV9oYXNfdm14 X3BsZSgpKSB7CisJCQlGSUVMRF9PRkZTRVQzMihQTEVfR0FQKTsKKwkJCUZJRUxEX09GRlNFVDMy KFBMRV9XSU5ET1cpOworCQl9CisJfQorfQorCitzdGF0aWMgaW5saW5lIHZvaWQgYXBwZW5kX2Zp ZWxkKHZvaWQpCit7CisjZGVmaW5lIEZJRUxEX09GRlNFVChmaWVsZCkgXAorCVZNQ1NJTkZPX0ZJ RUxEKGZpZWxkLCB2bWNzX3JlYWRsKGZpZWxkKSk7CisKKwlGSUVMRF9PRkZTRVQoQ1IwX0dVRVNU X0hPU1RfTUFTSyk7CisJRklFTERfT0ZGU0VUKENSNF9HVUVTVF9IT1NUX01BU0spOworCUZJRUxE X09GRlNFVChDUjBfUkVBRF9TSEFET1cpOworCUZJRUxEX09GRlNFVChDUjRfUkVBRF9TSEFET1cp OworCUZJRUxEX09GRlNFVChDUjNfVEFSR0VUX1ZBTFVFMCk7CisJRklFTERfT0ZGU0VUKENSM19U QVJHRVRfVkFMVUUxKTsKKwlGSUVMRF9PRkZTRVQoQ1IzX1RBUkdFVF9WQUxVRTIpOworCUZJRUxE X09GRlNFVChDUjNfVEFSR0VUX1ZBTFVFMyk7CisJRklFTERfT0ZGU0VUKEVYSVRfUVVBTElGSUNB VElPTik7CisJRklFTERfT0ZGU0VUKEdVRVNUX0xJTkVBUl9BRERSRVNTKTsKKwlGSUVMRF9PRkZT RVQoR1VFU1RfQ1IwKTsKKwlGSUVMRF9PRkZTRVQoR1VFU1RfQ1IzKTsKKwlGSUVMRF9PRkZTRVQo R1VFU1RfQ1I0KTsKKwlGSUVMRF9PRkZTRVQoR1VFU1RfRVNfQkFTRSk7CisJRklFTERfT0ZGU0VU KEdVRVNUX0NTX0JBU0UpOworCUZJRUxEX09GRlNFVChHVUVTVF9TU19CQVNFKTsKKwlGSUVMRF9P RkZTRVQoR1VFU1RfRFNfQkFTRSk7CisJRklFTERfT0ZGU0VUKEdVRVNUX0ZTX0JBU0UpOworCUZJ RUxEX09GRlNFVChHVUVTVF9HU19CQVNFKTsKKwlGSUVMRF9PRkZTRVQoR1VFU1RfTERUUl9CQVNF KTsKKwlGSUVMRF9PRkZTRVQoR1VFU1RfVFJfQkFTRSk7CisJRklFTERfT0ZGU0VUKEdVRVNUX0dE VFJfQkFTRSk7CisJRklFTERfT0ZGU0VUKEdVRVNUX0lEVFJfQkFTRSk7CisJRklFTERfT0ZGU0VU KEdVRVNUX0RSNyk7CisJRklFTERfT0ZGU0VUKEdVRVNUX1JTUCk7CisJRklFTERfT0ZGU0VUKEdV RVNUX1JJUCk7CisJRklFTERfT0ZGU0VUKEdVRVNUX1JGTEFHUyk7CisJRklFTERfT0ZGU0VUKEdV RVNUX1BFTkRJTkdfREJHX0VYQ0VQVElPTlMpOworCUZJRUxEX09GRlNFVChHVUVTVF9TWVNFTlRF Ul9FU1ApOworCUZJRUxEX09GRlNFVChHVUVTVF9TWVNFTlRFUl9FSVApOworCUZJRUxEX09GRlNF VChIT1NUX0NSMCk7CisJRklFTERfT0ZGU0VUKEhPU1RfQ1IzKTsKKwlGSUVMRF9PRkZTRVQoSE9T VF9DUjQpOworCUZJRUxEX09GRlNFVChIT1NUX0ZTX0JBU0UpOworCUZJRUxEX09GRlNFVChIT1NU X0dTX0JBU0UpOworCUZJRUxEX09GRlNFVChIT1NUX1RSX0JBU0UpOworCUZJRUxEX09GRlNFVChI T1NUX0dEVFJfQkFTRSk7CisJRklFTERfT0ZGU0VUKEhPU1RfSURUUl9CQVNFKTsKKwlGSUVMRF9P RkZTRVQoSE9TVF9JQTMyX1NZU0VOVEVSX0VTUCk7CisJRklFTERfT0ZGU0VUKEhPU1RfSUEzMl9T WVNFTlRFUl9FSVApOworCUZJRUxEX09GRlNFVChIT1NUX1JTUCk7CisJRklFTERfT0ZGU0VUKEhP U1RfUklQKTsKK30KKworLyoKKyAqIGFsbG9jX3ZtY3NpbmZvIHdpbGwgYmUgY2FsbGVkIGF0IHRo ZSBpbml0aWFsaXphdGlvbiBvZgorICoga3ZtX2ludGVsIG1vZHVsZSB0byBmaWxsIFZNQ1NJTkZP LiBUaGUgVk1DU0lORk8gY29udGFpbnMKKyAqIGEgVk1DUyByZXZpc2lvbiBpZGVudGlmaWVyIGFu ZCBlbmNvZGVkIG9mZnNldHMgb2YgZmllbGRzLgorICoKKyAqIE5vdGUsIG9mZnNldHMgb2YgZmll bGRzIGJlbG93IHdpbGwgbm90IGJlIGZpbGxlZCBpbnRvCisgKiBWTUNTSU5GTzoKKyAqIDEuIGZp ZWxkcyBkZWZpbmVkIGluIEludGVsIHNwZWNpZmljYXRpb24gKEludGVswq4gNjQgYW5kCisgKiAg ICBJQS0zMiBBcmNoaXRlY3R1cmVzIFNvZnR3YXJlIERldmVsb3BlcuKAmXMgTWFudWFsLCBWb2x1 bWUKKyAqICAgIDNDKSBidXQgbm90IGRlZmluZWQgaW4gKnZtY3NfZmllbGQqLgorICogMi4gZmll bGRzIGRvbid0IGV4aXN0IGJlY2F1c2UgdGhlaXIgY29ycmVzcG9uZGluZworICogICAgY29udHJv bCBiaXRzIGFyZSBub3Qgc2V0LgorICovCitzdGF0aWMgX19pbml0IHZvaWQgYWxsb2Nfdm1jc2lu Zm8odm9pZCkKK3sKKy8qCisgKiBUaGUgZmlyc3QgOCBieXRlcyBpbiB2bWNzIHJlZ2lvbiBhcmUg Zm9yCisgKiAgIFZNQ1MgcmV2aXNpb24gaWRlbnRpZmllcgorICogICBWTVgtYWJvcnQgaW5kaWNh dG9yCisgKi8KKyNkZWZpbmUgRklFTERfU1RBUlQgKDgpCisKKwlpbnQgb2Zmc2V0LCBmbGFnOwor CXN0cnVjdCB2bWNzICp2bWNzOworCXU2NCBvbGRfbXNyLCB0ZXN0X2JpdHM7CisKKwlmbGFnID0g MDsKKworCWlmICh2bWNzaW5mb19zaXplKQorCQlyZXR1cm47CisKKwl2bWNzID0gYWxsb2Nfdm1j cygpOworCWlmICghdm1jcykgeworCQlyZXR1cm47CisJfQorCisJcmRtc3JsKE1TUl9JQTMyX0ZF QVRVUkVfQ09OVFJPTCwgb2xkX21zcik7CisKKwl0ZXN0X2JpdHMgPSBGRUFUVVJFX0NPTlRST0xf TE9DS0VEOworCXRlc3RfYml0cyB8PSBGRUFUVVJFX0NPTlRST0xfVk1YT05fRU5BQkxFRF9PVVRT SURFX1NNWDsKKwlpZiAodGJvb3RfZW5hYmxlZCgpKQorCQl0ZXN0X2JpdHMgfD0gRkVBVFVSRV9D T05UUk9MX1ZNWE9OX0VOQUJMRURfSU5TSURFX1NNWDsKKwlpZiAoKG9sZF9tc3IgJiB0ZXN0X2Jp dHMpICE9IHRlc3RfYml0cykKKwkJd3Jtc3JsKE1TUl9JQTMyX0ZFQVRVUkVfQ09OVFJPTCwgb2xk X21zciB8IHRlc3RfYml0cyk7CisKKwlmbGFnID0gcmVhZF9jcjQoKSAmIFg4Nl9DUjRfVk1YRTsK KwlpZiAoIWZsYWcpCisJCXdyaXRlX2NyNChyZWFkX2NyNCgpIHwgWDg2X0NSNF9WTVhFKTsKKwor CWt2bV9jcHVfdm14b24oX19wYShwZXJfY3B1KHZteGFyZWEsIHJhd19zbXBfcHJvY2Vzc29yX2lk KCkpKSk7CisJdm1jc19sb2FkKHZtY3MpOworCisJVk1DU0lORk9fUkVWSVNJT05fSUQodm1jcy0+ cmV2aXNpb25faWQpOworCisJLyoKKwkgKiBXcml0ZSBlbmNvZGVkIG9mZnNldHMgaW50byBWTUNT IGRhdGEgZm9yIGxhdGVyIHZtY3NfcmVhZC4KKwkgKi8KKwlmb3IgKG9mZnNldCA9IEZJRUxEX1NU QVJUOyBvZmZzZXQgPCB2bWNzX2NvbmZpZy5zaXplOworCSAgICAgb2Zmc2V0ICs9IHNpemVvZih1 MTYpKQorCQkqKHUxNiAqKSgoY2hhciAqKXZtY3MgKyBvZmZzZXQpID0gRU5DT0RJTkdfT0ZGU0VU KG9mZnNldCk7CisKKwlhcHBlbmRfY29udHJvbF9maWVsZCgpOworCisJdm1jc193cml0ZTMyKFBJ Tl9CQVNFRF9WTV9FWEVDX0NPTlRST0wsCisJCSAgICAgdm1jc19jb25maWcucGluX2Jhc2VkX2V4 ZWNfY3RybCk7CisJdm1jc193cml0ZTMyKENQVV9CQVNFRF9WTV9FWEVDX0NPTlRST0wsCisJCSAg ICAgdm1jc19jb25maWcuY3B1X2Jhc2VkX2V4ZWNfY3RybCk7CisJaWYgKGNwdV9oYXNfc2Vjb25k YXJ5X2V4ZWNfY3RybHMoKSkgeworCQl2bWNzX3dyaXRlMzIoU0VDT05EQVJZX1ZNX0VYRUNfQ09O VFJPTCwKKwkJCSAgICAgdm1jc19jb25maWcuY3B1X2Jhc2VkXzJuZF9leGVjX2N0cmwpOworCX0K Kwl2bWNzX3dyaXRlMzIoVk1fRVhJVF9DT05UUk9MUywgdm1jc19jb25maWcudm1leGl0X2N0cmwp OworCXZtY3Nfd3JpdGUzMihWTV9FTlRSWV9DT05UUk9MUywgdm1jc19jb25maWcudm1lbnRyeV9j dHJsKTsKKworCWFwcGVuZF9maWVsZDE2KCk7CisJYXBwZW5kX2ZpZWxkNjQoKTsKKwlhcHBlbmRf ZmllbGQzMigpOworCWFwcGVuZF9maWVsZCgpOworCisJdXBkYXRlX3ZtY3NpbmZvX25vdGUoKTsK KworCXZtY3NfY2xlYXIodm1jcyk7CisJa3ZtX2NwdV92bXhvZmYoKTsKKwlpZiAoIWZsYWcpCisJ CXdyaXRlX2NyNChyZWFkX2NyNCgpICYgflg4Nl9DUjRfVk1YRSk7CisJd3Jtc3JsKE1TUl9JQTMy X0ZFQVRVUkVfQ09OVFJPTCwgb2xkX21zcik7CisKKwlmcmVlX3ZtY3Modm1jcyk7Cit9CisKIHN0 YXRpYyBfX2luaXQgaW50IGhhcmR3YXJlX3NldHVwKHZvaWQpCiB7CiAJaWYgKHNldHVwX3ZtY3Nf Y29uZmlnKCZ2bWNzX2NvbmZpZykgPCAwKQpAQCAtNzIyNyw2ICs3NTc1LDggQEAgc3RhdGljIGlu dCBfX2luaXQgdm14X2luaXQodm9pZCkKIAlpZiAocikKIAkJZ290byBvdXQzOwogCisJYWxsb2Nf dm1jc2luZm8oKTsKKwogCXZteF9kaXNhYmxlX2ludGVyY2VwdF9mb3JfbXNyKE1TUl9GU19CQVNF LCBmYWxzZSk7CiAJdm14X2Rpc2FibGVfaW50ZXJjZXB0X2Zvcl9tc3IoTVNSX0dTX0JBU0UsIGZh bHNlKTsKIAl2bXhfZGlzYWJsZV9pbnRlcmNlcHRfZm9yX21zcihNU1JfS0VSTkVMX0dTX0JBU0Us IHRydWUpOwotLSAKMS43LjEKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCmtleGVjIG1haWxpbmcgbGlzdAprZXhlY0BsaXN0cy5pbmZyYWRlYWQub3JnCmh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8va2V4ZWMK From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhangyanfei Subject: [PATCH 2/4] KVM: VMX: Add functions to fill VMCSINFO Date: Wed, 11 Apr 2012 09:50:29 +0800 Message-ID: <4F84E365.10201@cn.fujitsu.com> References: <4F84E0DF.8040206@cn.fujitsu.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: ebiederm@xmission.com, luto@mit.edu, joerg.roedel@amd.com, dzickus@redhat.com, paul.gortmaker@windriver.com, gregkh@suse.de, ludwig.nussel@suse.de, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kexec@lists.infradead.org To: avi@redhat.com, mtosatti@redhat.com Return-path: Received: from cn.fujitsu.com ([222.73.24.84]:13027 "EHLO song.cn.fujitsu.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1754009Ab2DKBup convert rfc822-to-8bit (ORCPT ); Tue, 10 Apr 2012 21:50:45 -0400 In-Reply-To: <4F84E0DF.8040206@cn.fujitsu.com> Sender: kvm-owner@vger.kernel.org List-ID: This patch is to implement the feature that at initialization of kvm_intel module, fills VMCSINFO with a VMCS revision identifier, and encoded offsets of VMCS fields. The reason why we put the VMCSINFO processing at the initialization of kvm_intel module is that it's dangerous to rob VMX resources while kvm module is loaded. Note, offsets of fields below will not be filled into VMCSINFO: 1. fields defined in Intel specification (Intel=C2=AE 64 and IA-32 Architectures Software Developer=E2=80=99s Manual, Volume 3C) but not defined in *vmcs_field*. 2. fields don't exist because their corresponding control bits are not set. Signed-off-by: zhangyanfei --- arch/x86/kvm/vmx.c | 350 ++++++++++++++++++++++++++++++++++++++++++++= ++++++++ 1 files changed, 350 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index ad85adf..e98fafa 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -41,6 +41,7 @@ #include #include #include +#include =20 #include "trace.h" =20 @@ -2599,6 +2600,353 @@ static __init int alloc_kvm_area(void) return 0; } =20 +/* + * For caculating offsets of fields in VMCS data, we index every 16-bi= t + * field by this kind of format: + * | --------- 16 bits ---------- | + * +-------------+-+------------+-+ + * | high 7 bits |1| low 7 bits |0| + * +-------------+-+------------+-+ + * In high byte, the lowest bit must be 1; In low byte, the lowest bit + * must be 0. The two bits are set like this in case indexes in VMCS + * data are read as big endian mode. + * The remaining 14 bits of the index indicate the real offset of the + * field. Because the size of a VMCS region is at most 4 KBytes, so + * 14 bits are enough to index the whole VMCS region. + * + * ENCODING_OFFSET: encode the offset into the index of this kind. + */ +#define OFFSET_HIGH_SHIFT (7) +#define OFFSET_LOW_MASK ((1 << OFFSET_HIGH_SHIFT) - 1) /* 0x7f */ +#define OFFSET_HIGH_MASK (OFFSET_LOW_MASK << OFFSET_HIGH_SHIFT) /* 0x= 3f80 */ +#define ENCODING_OFFSET(offset) \ + ((((offset) & OFFSET_LOW_MASK) << 1) + \ + ((((offset) & OFFSET_HIGH_MASK) << 2) | 0x100)) + +/* + * We separate these five control fields from other fields + * because some fields only exist on processors that support + * the 1-setting of control bits in the five control fields. + */ +static inline void append_control_field(void) +{ +#define CONTROL_FIELD_OFFSET(field) \ + VMCSINFO_FIELD32(field, vmcs_read32(field)) + + CONTROL_FIELD_OFFSET(PIN_BASED_VM_EXEC_CONTROL); + CONTROL_FIELD_OFFSET(CPU_BASED_VM_EXEC_CONTROL); + if (cpu_has_secondary_exec_ctrls()) { + CONTROL_FIELD_OFFSET(SECONDARY_VM_EXEC_CONTROL); + } + CONTROL_FIELD_OFFSET(VM_EXIT_CONTROLS); + CONTROL_FIELD_OFFSET(VM_ENTRY_CONTROLS); +} + +static inline void append_field16(void) +{ +#define FIELD_OFFSET16(field) \ + VMCSINFO_FIELD16(field, vmcs_read16(field)); + + FIELD_OFFSET16(GUEST_ES_SELECTOR); + FIELD_OFFSET16(GUEST_CS_SELECTOR); + FIELD_OFFSET16(GUEST_SS_SELECTOR); + FIELD_OFFSET16(GUEST_DS_SELECTOR); + FIELD_OFFSET16(GUEST_FS_SELECTOR); + FIELD_OFFSET16(GUEST_GS_SELECTOR); + FIELD_OFFSET16(GUEST_LDTR_SELECTOR); + FIELD_OFFSET16(GUEST_TR_SELECTOR); + FIELD_OFFSET16(HOST_ES_SELECTOR); + FIELD_OFFSET16(HOST_CS_SELECTOR); + FIELD_OFFSET16(HOST_SS_SELECTOR); + FIELD_OFFSET16(HOST_DS_SELECTOR); + FIELD_OFFSET16(HOST_FS_SELECTOR); + FIELD_OFFSET16(HOST_GS_SELECTOR); + FIELD_OFFSET16(HOST_TR_SELECTOR); +} + +static inline void append_field64(void) +{ +#define FIELD_OFFSET64(field) \ + VMCSINFO_FIELD64(field, vmcs_read64(field)); + + FIELD_OFFSET64(IO_BITMAP_A); + FIELD_OFFSET64(IO_BITMAP_A_HIGH); + FIELD_OFFSET64(IO_BITMAP_B); + FIELD_OFFSET64(IO_BITMAP_B_HIGH); + FIELD_OFFSET64(VM_EXIT_MSR_STORE_ADDR); + FIELD_OFFSET64(VM_EXIT_MSR_STORE_ADDR_HIGH); + FIELD_OFFSET64(VM_EXIT_MSR_LOAD_ADDR); + FIELD_OFFSET64(VM_EXIT_MSR_LOAD_ADDR_HIGH); + FIELD_OFFSET64(VM_ENTRY_MSR_LOAD_ADDR); + FIELD_OFFSET64(VM_ENTRY_MSR_LOAD_ADDR_HIGH); + FIELD_OFFSET64(TSC_OFFSET); + FIELD_OFFSET64(TSC_OFFSET_HIGH); + FIELD_OFFSET64(VMCS_LINK_POINTER); + FIELD_OFFSET64(VMCS_LINK_POINTER_HIGH); + FIELD_OFFSET64(GUEST_IA32_DEBUGCTL); + FIELD_OFFSET64(GUEST_IA32_DEBUGCTL_HIGH); + + if (cpu_has_vmx_msr_bitmap()) { + FIELD_OFFSET64(MSR_BITMAP); + FIELD_OFFSET64(MSR_BITMAP_HIGH); + } + + if (cpu_has_vmx_tpr_shadow()) { + FIELD_OFFSET64(VIRTUAL_APIC_PAGE_ADDR); + FIELD_OFFSET64(VIRTUAL_APIC_PAGE_ADDR_HIGH); + } + + if (cpu_has_secondary_exec_ctrls()) { + if (vmcs_config.cpu_based_2nd_exec_ctrl & + SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) { + FIELD_OFFSET64(APIC_ACCESS_ADDR); + FIELD_OFFSET64(APIC_ACCESS_ADDR_HIGH); + } + if (cpu_has_vmx_ept()) { + FIELD_OFFSET64(EPT_POINTER); + FIELD_OFFSET64(EPT_POINTER_HIGH); + FIELD_OFFSET64(GUEST_PHYSICAL_ADDRESS); + FIELD_OFFSET64(GUEST_PHYSICAL_ADDRESS_HIGH); + FIELD_OFFSET64(GUEST_PDPTR0); + FIELD_OFFSET64(GUEST_PDPTR0_HIGH); + FIELD_OFFSET64(GUEST_PDPTR1); + FIELD_OFFSET64(GUEST_PDPTR1_HIGH); + FIELD_OFFSET64(GUEST_PDPTR2); + FIELD_OFFSET64(GUEST_PDPTR2_HIGH); + FIELD_OFFSET64(GUEST_PDPTR3); + FIELD_OFFSET64(GUEST_PDPTR3_HIGH); + } + } + + if (vmcs_config.vmexit_ctrl & VM_EXIT_SAVE_IA32_PAT || \ + vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { + FIELD_OFFSET64(GUEST_IA32_PAT); + FIELD_OFFSET64(GUEST_IA32_PAT_HIGH); + } + + if (vmcs_config.vmexit_ctrl & VM_EXIT_SAVE_IA32_EFER || \ + vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER) { + FIELD_OFFSET64(GUEST_IA32_EFER); + FIELD_OFFSET64(GUEST_IA32_EFER_HIGH); + } + + if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) { + FIELD_OFFSET64(GUEST_IA32_PERF_GLOBAL_CTRL); + FIELD_OFFSET64(GUEST_IA32_PERF_GLOBAL_CTRL_HIGH); + } + + if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { + FIELD_OFFSET64(HOST_IA32_PAT); + FIELD_OFFSET64(HOST_IA32_PAT_HIGH); + } + + if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_EFER) { + FIELD_OFFSET64(HOST_IA32_EFER); + FIELD_OFFSET64(HOST_IA32_EFER_HIGH); + } + + if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) { + FIELD_OFFSET64(HOST_IA32_PERF_GLOBAL_CTRL); + FIELD_OFFSET64(HOST_IA32_PERF_GLOBAL_CTRL_HIGH); + } +} + +static inline void append_field32(void) +{ +#define FIELD_OFFSET32(field) \ + VMCSINFO_FIELD32(field, vmcs_read32(field)); + + FIELD_OFFSET32(EXCEPTION_BITMAP); + FIELD_OFFSET32(PAGE_FAULT_ERROR_CODE_MASK); + FIELD_OFFSET32(PAGE_FAULT_ERROR_CODE_MATCH); + FIELD_OFFSET32(CR3_TARGET_COUNT); + FIELD_OFFSET32(VM_EXIT_MSR_STORE_COUNT); + FIELD_OFFSET32(VM_EXIT_MSR_LOAD_COUNT); + FIELD_OFFSET32(VM_ENTRY_MSR_LOAD_COUNT); + FIELD_OFFSET32(VM_ENTRY_INTR_INFO_FIELD); + FIELD_OFFSET32(VM_ENTRY_EXCEPTION_ERROR_CODE); + FIELD_OFFSET32(VM_ENTRY_INSTRUCTION_LEN); + FIELD_OFFSET32(VM_INSTRUCTION_ERROR); + FIELD_OFFSET32(VM_EXIT_REASON); + FIELD_OFFSET32(VM_EXIT_INTR_INFO); + FIELD_OFFSET32(VM_EXIT_INTR_ERROR_CODE); + FIELD_OFFSET32(IDT_VECTORING_INFO_FIELD); + FIELD_OFFSET32(IDT_VECTORING_ERROR_CODE); + FIELD_OFFSET32(VM_EXIT_INSTRUCTION_LEN); + FIELD_OFFSET32(VMX_INSTRUCTION_INFO); + FIELD_OFFSET32(GUEST_ES_LIMIT); + FIELD_OFFSET32(GUEST_CS_LIMIT); + FIELD_OFFSET32(GUEST_SS_LIMIT); + FIELD_OFFSET32(GUEST_DS_LIMIT); + FIELD_OFFSET32(GUEST_FS_LIMIT); + FIELD_OFFSET32(GUEST_GS_LIMIT); + FIELD_OFFSET32(GUEST_LDTR_LIMIT); + FIELD_OFFSET32(GUEST_TR_LIMIT); + FIELD_OFFSET32(GUEST_GDTR_LIMIT); + FIELD_OFFSET32(GUEST_IDTR_LIMIT); + FIELD_OFFSET32(GUEST_ES_AR_BYTES); + FIELD_OFFSET32(GUEST_CS_AR_BYTES); + FIELD_OFFSET32(GUEST_SS_AR_BYTES); + FIELD_OFFSET32(GUEST_DS_AR_BYTES); + FIELD_OFFSET32(GUEST_FS_AR_BYTES); + FIELD_OFFSET32(GUEST_GS_AR_BYTES); + FIELD_OFFSET32(GUEST_LDTR_AR_BYTES); + FIELD_OFFSET32(GUEST_TR_AR_BYTES); + FIELD_OFFSET32(GUEST_INTERRUPTIBILITY_INFO); + FIELD_OFFSET32(GUEST_ACTIVITY_STATE); + FIELD_OFFSET32(GUEST_SYSENTER_CS); + FIELD_OFFSET32(HOST_IA32_SYSENTER_CS); + + if (cpu_has_vmx_tpr_shadow()) { + FIELD_OFFSET32(TPR_THRESHOLD); + } + if (cpu_has_secondary_exec_ctrls()) { + if (cpu_has_vmx_ple()) { + FIELD_OFFSET32(PLE_GAP); + FIELD_OFFSET32(PLE_WINDOW); + } + } +} + +static inline void append_field(void) +{ +#define FIELD_OFFSET(field) \ + VMCSINFO_FIELD(field, vmcs_readl(field)); + + FIELD_OFFSET(CR0_GUEST_HOST_MASK); + FIELD_OFFSET(CR4_GUEST_HOST_MASK); + FIELD_OFFSET(CR0_READ_SHADOW); + FIELD_OFFSET(CR4_READ_SHADOW); + FIELD_OFFSET(CR3_TARGET_VALUE0); + FIELD_OFFSET(CR3_TARGET_VALUE1); + FIELD_OFFSET(CR3_TARGET_VALUE2); + FIELD_OFFSET(CR3_TARGET_VALUE3); + FIELD_OFFSET(EXIT_QUALIFICATION); + FIELD_OFFSET(GUEST_LINEAR_ADDRESS); + FIELD_OFFSET(GUEST_CR0); + FIELD_OFFSET(GUEST_CR3); + FIELD_OFFSET(GUEST_CR4); + FIELD_OFFSET(GUEST_ES_BASE); + FIELD_OFFSET(GUEST_CS_BASE); + FIELD_OFFSET(GUEST_SS_BASE); + FIELD_OFFSET(GUEST_DS_BASE); + FIELD_OFFSET(GUEST_FS_BASE); + FIELD_OFFSET(GUEST_GS_BASE); + FIELD_OFFSET(GUEST_LDTR_BASE); + FIELD_OFFSET(GUEST_TR_BASE); + FIELD_OFFSET(GUEST_GDTR_BASE); + FIELD_OFFSET(GUEST_IDTR_BASE); + FIELD_OFFSET(GUEST_DR7); + FIELD_OFFSET(GUEST_RSP); + FIELD_OFFSET(GUEST_RIP); + FIELD_OFFSET(GUEST_RFLAGS); + FIELD_OFFSET(GUEST_PENDING_DBG_EXCEPTIONS); + FIELD_OFFSET(GUEST_SYSENTER_ESP); + FIELD_OFFSET(GUEST_SYSENTER_EIP); + FIELD_OFFSET(HOST_CR0); + FIELD_OFFSET(HOST_CR3); + FIELD_OFFSET(HOST_CR4); + FIELD_OFFSET(HOST_FS_BASE); + FIELD_OFFSET(HOST_GS_BASE); + FIELD_OFFSET(HOST_TR_BASE); + FIELD_OFFSET(HOST_GDTR_BASE); + FIELD_OFFSET(HOST_IDTR_BASE); + FIELD_OFFSET(HOST_IA32_SYSENTER_ESP); + FIELD_OFFSET(HOST_IA32_SYSENTER_EIP); + FIELD_OFFSET(HOST_RSP); + FIELD_OFFSET(HOST_RIP); +} + +/* + * alloc_vmcsinfo will be called at the initialization of + * kvm_intel module to fill VMCSINFO. The VMCSINFO contains + * a VMCS revision identifier and encoded offsets of fields. + * + * Note, offsets of fields below will not be filled into + * VMCSINFO: + * 1. fields defined in Intel specification (Intel=C2=AE 64 and + * IA-32 Architectures Software Developer=E2=80=99s Manual, Volume + * 3C) but not defined in *vmcs_field*. + * 2. fields don't exist because their corresponding + * control bits are not set. + */ +static __init void alloc_vmcsinfo(void) +{ +/* + * The first 8 bytes in vmcs region are for + * VMCS revision identifier + * VMX-abort indicator + */ +#define FIELD_START (8) + + int offset, flag; + struct vmcs *vmcs; + u64 old_msr, test_bits; + + flag =3D 0; + + if (vmcsinfo_size) + return; + + vmcs =3D alloc_vmcs(); + if (!vmcs) { + return; + } + + rdmsrl(MSR_IA32_FEATURE_CONTROL, old_msr); + + test_bits =3D FEATURE_CONTROL_LOCKED; + test_bits |=3D FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; + if (tboot_enabled()) + test_bits |=3D FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; + if ((old_msr & test_bits) !=3D test_bits) + wrmsrl(MSR_IA32_FEATURE_CONTROL, old_msr | test_bits); + + flag =3D read_cr4() & X86_CR4_VMXE; + if (!flag) + write_cr4(read_cr4() | X86_CR4_VMXE); + + kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); + vmcs_load(vmcs); + + VMCSINFO_REVISION_ID(vmcs->revision_id); + + /* + * Write encoded offsets into VMCS data for later vmcs_read. + */ + for (offset =3D FIELD_START; offset < vmcs_config.size; + offset +=3D sizeof(u16)) + *(u16 *)((char *)vmcs + offset) =3D ENCODING_OFFSET(offset); + + append_control_field(); + + vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, + vmcs_config.pin_based_exec_ctrl); + vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, + vmcs_config.cpu_based_exec_ctrl); + if (cpu_has_secondary_exec_ctrls()) { + vmcs_write32(SECONDARY_VM_EXEC_CONTROL, + vmcs_config.cpu_based_2nd_exec_ctrl); + } + vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); + vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); + + append_field16(); + append_field64(); + append_field32(); + append_field(); + + update_vmcsinfo_note(); + + vmcs_clear(vmcs); + kvm_cpu_vmxoff(); + if (!flag) + write_cr4(read_cr4() & ~X86_CR4_VMXE); + wrmsrl(MSR_IA32_FEATURE_CONTROL, old_msr); + + free_vmcs(vmcs); +} + static __init int hardware_setup(void) { if (setup_vmcs_config(&vmcs_config) < 0) @@ -7227,6 +7575,8 @@ static int __init vmx_init(void) if (r) goto out3; =20 + alloc_vmcsinfo(); + vmx_disable_intercept_for_msr(MSR_FS_BASE, false); vmx_disable_intercept_for_msr(MSR_GS_BASE, false); vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); --=20 1.7.1