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Message-ID: <4F8C4D4E.4060900@gmail.com>
Date:   Mon, 16 Apr 2012 09:48:14 -0700
From:   David Daney <ddaney.cavm@gmail.com>
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To:     Yong Zhang <yong.zhang0@gmail.com>
CC:     linux-mips@linux-mips.org, Yong Zhang <yong.zhang@windriver.com>,
        David Daney <ddaney@caviumnetworks.com>,
        Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH] MIPS: cavium: Don't enable irq in ->init__secondary()
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On 04/16/2012 12:25 AM, Yong Zhang wrote:
> From: Yong Zhang<yong.zhang@windriver.com>
>
> Too early to enable irq will break some following action,
> such as notify_cpu_starting().

Can you be more specific about what breaks?

>
> I don't get side effect with this patch.

Without this, where do irqs get enabled on the secondary CPUs?

>
> Signed-off-by: Yong Zhang<yong.zhang0@gmail.com>
> Cc: David Daney<ddaney@caviumnetworks.com>
> Cc: Ralf Baechle<ralf@linux-mips.org>
> ---
>   arch/mips/cavium-octeon/smp.c |    1 -
>   1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
> index 97e7ce9..7e65c88 100644
> --- a/arch/mips/cavium-octeon/smp.c
> +++ b/arch/mips/cavium-octeon/smp.c
> @@ -185,7 +185,6 @@ static void __cpuinit octeon_init_secondary(void)
>   	octeon_init_cvmcount();
>
>   	octeon_irq_setup_secondary();
> -	raw_local_irq_enable();
>   }
>
>   /**