diff for duplicates of <4F8DBA51.4040205@freescale.com> diff --git a/a/1.txt b/N1/1.txt index 3f7a9fd..a794961 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -7,12 +7,12 @@ On 04/17/2012 01:44 PM, Simon Glass wrote: >>> >>> On Fri, Apr 13, 2012 at 2:05 PM, Stephen Warren <swarren@wwwdotorg.org> wrote: >>>> On 04/13/2012 12:29 PM, Simon Glass wrote: ->>>>> +nand-controller@0x70008000 { +>>>>> +nand-controller at 0x70008000 { >>>>> + compatible = "nvidia,tegra20-nand"; >>>>> + wp-gpios = <&gpio 59 0>; /* PH3 */ >>>>> + nvidia,width = <8>; >>>>> + nvidia,timing = <26 100 20 80 20 10 12 10 70>; ->>>>> + nand@0 { +>>>>> + nand at 0 { >>>>> + compatible = "hynix,hy27uf4g2b", "nand-flash"; >>>> >>>> The TRM says there can be up to 8 chip selects. Don't the NAND device diff --git a/a/content_digest b/N1/content_digest index 9d4c4a0..78dd5da 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,14 +5,9 @@ "ref\04F8DB8A9.4060506@freescale.com\0" "ref\0CAPnjgZ0OCibwkMRP4OLCou_vF8pOxh_Zgs1GwD_Zu4jWfSSfbA@mail.gmail.com\0" "From\0Scott Wood <scottwood@freescale.com>\0" - "Subject\0Re: [PATCH v2 4/7] tegra: fdt: Add NAND controller binding and definitions\0" + "Subject\0[U-Boot] [PATCH v2 4/7] tegra: fdt: Add NAND controller binding and definitions\0" "Date\0Tue, 17 Apr 2012 13:45:37 -0500\0" - "To\0Simon Glass <sjg@chromium.org>\0" - "Cc\0Devicetree@theia.denx.de" - Discuss <devicetree-discuss@lists.ozlabs.org> - U-Boot Mailing List <u-boot@lists.denx.de> - Jerry Van Baren <vanbaren@cideas.com> - " Tom Warren <twarren@nvidia.com>\0" + "To\0u-boot@lists.denx.de\0" "\00:1\0" "b\0" "On 04/17/2012 01:44 PM, Simon Glass wrote:\n" @@ -24,12 +19,12 @@ ">>>\n" ">>> On Fri, Apr 13, 2012 at 2:05 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:\n" ">>>> On 04/13/2012 12:29 PM, Simon Glass wrote:\n" - ">>>>> +nand-controller@0x70008000 {\n" + ">>>>> +nand-controller at 0x70008000 {\n" ">>>>> + compatible = \"nvidia,tegra20-nand\";\n" ">>>>> + wp-gpios = <&gpio 59 0>; /* PH3 */\n" ">>>>> + nvidia,width = <8>;\n" ">>>>> + nvidia,timing = <26 100 20 80 20 10 12 10 70>;\n" - ">>>>> + nand@0 {\n" + ">>>>> + nand at 0 {\n" ">>>>> + compatible = \"hynix,hy27uf4g2b\", \"nand-flash\";\n" ">>>>\n" ">>>> The TRM says there can be up to 8 chip selects. Don't the NAND device\n" @@ -50,4 +45,4 @@ "\n" -Scott -7ce5582c675a6db697b07412bfda584f913c99b17be98a7f8fa0e1f190c63d2b +dfd1fc764051cf1fd663a870b0fda67397c7bee89cf7d0c0a672f7a77dc27c59
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