From mboxrd@z Thu Jan  1 00:00:00 1970
From: =?ISO-8859-1?Q?Christian_K=F6nig?= <deathsimple@vodafone.de>
Subject: Re: Re: [PATCH 2/4] drm/radeon: convert fence to uint64_t
Date: Thu, 03 May 2012 13:39:49 +0200
Message-ID: <4FA26E85.8020303@vodafone.de>
References: <1335990013-5877-1-git-send-email-j.glisse@gmail.com>
	<1335990013-5877-3-git-send-email-j.glisse@gmail.com>
	<1336029696.17679.43.camel@thor.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"; Format="flowed"
Content-Transfer-Encoding: quoted-printable
Return-path: <dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org>
Received: from outgoing.email.vodafone.de (outgoing.email.vodafone.de
	[139.7.28.128])
	by gabe.freedesktop.org (Postfix) with ESMTP id AF8CA9F03D
	for <dri-devel@lists.freedesktop.org>;
	Thu,  3 May 2012 04:39:53 -0700 (PDT)
In-Reply-To: <1336029696.17679.43.camel@thor.local>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/dri-devel>,
	<mailto:dri-devel-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/dri-devel>
List-Post: <mailto:dri-devel@lists.freedesktop.org>
List-Help: <mailto:dri-devel-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/dri-devel>,
	<mailto:dri-devel-request@lists.freedesktop.org?subject=subscribe>
Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org
Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org
To: =?ISO-8859-1?Q?Michel_D=E4nzer?= <michel@daenzer.net>
Cc: dri-devel@lists.freedesktop.org
List-Id: dri-devel@lists.freedesktop.org

On 03.05.2012 09:21, Michel D=E4nzer wrote:
> On Mit, 2012-05-02 at 16:20 -0400, j.glisse@gmail.com wrote:
>> From: Jerome Glisse<jglisse@redhat.com>
>>
>> This convert fence to use uint64_t sequence number intention is
>> to use the fact that uin64_t is big enough that we don't need to
>> care about wrap around.
>>
>> Tested with and without writeback using 0xFFFFF000 as initial
>> fence sequence and thus allowing to test the wrap around from
>> 32bits to 64bits.
>>
>> Signed-off-by: Jerome Glisse<jglisse@redhat.com>
> [...]
>
>> diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/rad=
eon/radeon_fence.c
>> index 7733429..6da1535 100644
>> --- a/drivers/gpu/drm/radeon/radeon_fence.c
>> +++ b/drivers/gpu/drm/radeon/radeon_fence.c
>> @@ -386,9 +388,9 @@ int radeon_fence_driver_start_ring(struct radeon_dev=
ice *rdev, int ring)
>>   			rdev->fence_drv[ring].scratch_reg -
>>   			rdev->scratch.reg_base;
>>   	}
>> -	rdev->fence_drv[ring].cpu_addr =3Drdev->wb.wb[index/4];
>> +	rdev->fence_drv[ring].cpu_addr =3Du64*)&rdev->wb.wb[index/4];
> Might want to ensure cpu_addr is 64 bit aligned, or there might be
> trouble on some architectures.
>
>
> With this change, Cayman cards will already use six scratch registers
> for the rings. It won't be possible to extend this scheme for even one
> additional ring, will it?

That won't work anyway, since not all rings can deal with 64 bit fences, =

so we need to still use 32 bit signaling and extend them to 64 bit while =

processing the fence value.

Already working on that.

Christian.