From: Alex Shi <alex.shi@intel.com>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: mgorman@suse.de, npiggin@gmail.com, tglx@linutronix.de,
mingo@redhat.com, hpa@zytor.com, arnd@arndb.de,
rostedt@goodmis.org, fweisbec@gmail.com, jeremy@goop.org,
gregkh@linuxfoundation.org, glommer@redhat.com, riel@redhat.com,
luto@mit.edu, avi@redhat.com, len.brown@intel.com,
dhowells@redhat.com, fenghua.yu@intel.com,
borislav.petkov@amd.com, yinghai@kernel.org, ak@linux.intel.com,
cpw@sgi.com, steiner@sgi.com, akpm@linux-foundation.org,
penberg@kernel.org, hughd@google.com, rientjes@google.com,
kosaki.motohiro@jp.fujitsu.com, n-horiguchi@ah.jp.nec.com,
paul.gortmaker@windriver.com, trenn@suse.de, tj@kernel.org,
oleg@redhat.com, axboe@kernel.dk, kamezawa.hiroyu@jp.fujitsu.com,
viro@zeniv.linux.org.uk, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/7] x86/tlb: add tlb flush all factor for specific CPUs
Date: Wed, 09 May 2012 10:03:41 +0800 [thread overview]
Message-ID: <4FA9D07D.8000401@intel.com> (raw)
In-Reply-To: <1336489685.16236.48.camel@twins>
On 05/08/2012 11:08 PM, Peter Zijlstra wrote:
> On Tue, 2012-05-08 at 22:03 +0800, Alex Shi wrote:
>> +void intel_tlb_flushall_factor_set(struct cpuinfo_x86 *c)
>> +{
>> + switch (c->x86_model) {
>> + case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
>> + tlb_flushall_factor = 0;
>> + break;
>
> Why isn't this is the bottom list of core chips?
It was tested. but the bottom list cpu was not tested.
>
>> + case 26: /* 45 nm nehalem, "Bloomfield" */
>> + case 30: /* 45 nm nehalem, "Lynnfield" */
>> + case 37: /* 32 nm nehalem, "Clarkdale" */
>> + case 44: /* 32 nm nehalem, "Gulftown" */
>> + case 46: /* 45 nm nehalem-ex, "Beckton" */
>> + tlb_flushall_factor = 64;
>> + break;
>> + case 42: /* SandyBridge */
>> + case 45: /* SandyBridge, "Romely-EP" */
>> + tlb_flushall_factor = 32;
>> + break;
>> + case 28: /* Atom */
>> + case 47: /* 32 nm Xeon E7 */
>
> This is a wsm-ex, right? Why isn't it listed with the other nehalems?
I don't know this. Thanks for this info
>
>> + case 14: /* 65 nm core solo/duo, "Yonah" */
>> + case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
>> + case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
>> + case 29: /* six-core 45 nm xeon "Dunnington" */
>
> So never use invlpg for Atom/Core/Core2?
Uh, I will remove the CPU list if they weren't tested.
>
>> + default:
>> + tlb_flushall_factor = 0;
>> + }
>> +}
>
>
>> @@ -364,7 +363,8 @@ flush_all:
>> act_entries = tlb_entries > mm->total_vm ?
>> mm->total_vm : tlb_entries;
>>
>> + if ((end - start)/PAGE_SIZE >
>> + act_entries/tlb_flushall_factor)
>
> You're doing an actual full division, wouldn't a shift be better?
Thanks!
next prev parent reply other threads:[~2012-05-09 2:05 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-08 14:03 [PATCH v3] TLB flush optimization Alex Shi
2012-05-08 14:03 ` [PATCH v3 1/7] x86/tlb_info: get last level TLB entry number of CPU Alex Shi
2012-05-08 14:03 ` [PATCH v3 2/7] x86/flush_tlb: try flush_tlb_single one by one in flush_tlb_range Alex Shi
2012-05-08 14:03 ` [PATCH v3 3/7] x86/tlb: fall back to flush all when meet a THP large page Alex Shi
2012-05-08 14:03 ` [PATCH v3 4/7] x86/tlb: add tlb flush all factor for specific CPUs Alex Shi
2012-05-08 15:08 ` Peter Zijlstra
2012-05-09 2:03 ` Alex Shi [this message]
2012-05-08 15:12 ` H. Peter Anvin
2012-05-09 2:10 ` Alex Shi
2012-05-08 15:15 ` H. Peter Anvin
2012-05-08 15:56 ` Andi Kleen
2012-05-08 16:40 ` H. Peter Anvin
2012-05-08 15:18 ` H. Peter Anvin
2012-05-09 1:41 ` Alex Shi
2012-05-08 14:03 ` [PATCH v3 5/7] x86/tlb: remove comments for tlb_flush_range implement suggestion Alex Shi
2012-05-09 8:22 ` Nick Piggin
2012-05-08 14:03 ` [PATCH v3 6/7] x86/tlb: optimizing flush_tlb_mm Alex Shi
2012-05-08 15:09 ` Peter Zijlstra
2012-05-08 14:03 ` [PATCH v3 7/7] x86/tlb: add tlb_flushall_factor into sysfs for user change Alex Shi
2012-05-08 15:11 ` Peter Zijlstra
2012-05-08 15:20 ` H. Peter Anvin
2012-05-08 15:25 ` Borislav Petkov
2012-05-08 15:31 ` H. Peter Anvin
2012-05-08 15:41 ` Borislav Petkov
2012-05-08 15:48 ` H. Peter Anvin
2012-05-08 16:10 ` Greg KH
2012-05-08 16:28 ` Borislav Petkov
2012-05-09 5:03 ` Alex Shi
2012-05-08 15:01 ` [PATCH v3] TLB flush optimization Peter Zijlstra
2012-05-09 1:58 ` Alex Shi
2012-05-09 23:45 ` Andi Kleen
2012-05-10 5:06 ` Alex Shi
2012-05-10 7:49 ` HATAYAMA Daisuke
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