From: Stephen Warren <swarren@wwwdotorg.org>
To: Hiroshi DOYU <hdoyu@nvidia.com>
Cc: linux-tegra@vger.kernel.org,
Grant Likely <grant.likely@secretlab.ca>,
Rob Herring <rob.herring@calxeda.com>,
Rob Landley <rob@landley.net>,
Thierry Reding <thierry.reding@avionic-design.de>,
Joerg Roedel <joerg.roedel@amd.com>,
Bharat Nihalani <bnihalani@nvidia.com>,
Vandana Salve <vsalve@nvidia.com>,
devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] iommu/tegra: gart: Fix register offset correctly
Date: Thu, 10 May 2012 11:28:28 -0600 [thread overview]
Message-ID: <4FABFABC.60407@wwwdotorg.org> (raw)
In-Reply-To: <1336635940-31068-1-git-send-email-hdoyu@nvidia.com>
On 05/10/2012 01:45 AM, Hiroshi DOYU wrote:
> DT passes the exact GART register ranges without any overlapping with
> MC register ranges. GART register offset needs to be adjusted by one
> passed by DT correctly.
>
> Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Joerg, I assume you'll take this patch through the iommu tree and I'll
take patch 2 through the Tegra tree?
prev parent reply other threads:[~2012-05-10 17:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-10 7:45 [PATCH 1/2] iommu/tegra: gart: Fix register offset correctly Hiroshi DOYU
2012-05-10 7:45 ` Hiroshi DOYU
[not found] ` <1336635940-31068-1-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-05-10 7:45 ` [PATCH 2/2] ARM: dt: tegra20.dtsi: Add GART node Hiroshi DOYU
2012-05-10 7:45 ` Hiroshi DOYU
2012-05-10 7:45 ` Hiroshi DOYU
2012-05-10 17:28 ` Stephen Warren [this message]
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