From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57070) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STAw4-000102-Lj for qemu-devel@nongnu.org; Sat, 12 May 2012 07:56:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1STAw3-00008M-1P for qemu-devel@nongnu.org; Sat, 12 May 2012 07:56:32 -0400 Received: from cantor2.suse.de ([195.135.220.15]:33167 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STAw2-00008F-RC for qemu-devel@nongnu.org; Sat, 12 May 2012 07:56:30 -0400 Message-ID: <4FAE4FE7.1040905@suse.de> Date: Sat, 12 May 2012 13:56:23 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko , blauwirbel@gmail.com Cc: qemu-devel@nongnu.org, Anthony Liguori Am 12.05.2012 11:15, schrieb Artyom Tarasenko: > Implement registers for clearing OBIO and PCI interrupts >=20 > Signed-off-by: Artyom Tarasenko Implementing new registers is a feature, not a 1.1 bugfix... Many of us would like to get patches committed and have to wait. /-F --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg