From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexey Kardashevskiy Subject: Re: [RFC PATCH] qemu spapr-pci: added IRQ list to PCIBus Date: Thu, 17 May 2012 13:39:45 +1000 Message-ID: <4FB47301.4060609@ozlabs.ru> References: <4FAE1171.1010806@ozlabs.ru> <20120514015830.GC30229@truffala.fritz.box> <4FB08867.9070103@ozlabs.ru> <1337200755.6954.269.camel@bling.home> <4FB45F8F.5000708@ozlabs.ru> <1337223641.30558.40.camel@pasglop> Mime-Version: 1.0 Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Cc: Alex Williamson , anthony@codemonkey.ws, Alex Graf , kvm@vger.kernel.org, qemu-devel@nongnu.org To: Benjamin Herrenschmidt Return-path: Received: from mail-pz0-f46.google.com ([209.85.210.46]:63364 "EHLO mail-pz0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760952Ab2EQDjy (ORCPT ); Wed, 16 May 2012 23:39:54 -0400 Received: by dady13 with SMTP id y13so1845884dad.19 for ; Wed, 16 May 2012 20:39:53 -0700 (PDT) In-Reply-To: <1337223641.30558.40.camel@pasglop> Sender: kvm-owner@vger.kernel.org List-ID: On 17/05/12 13:00, Benjamin Herrenschmidt wrote: > On Thu, 2012-05-17 at 12:16 +1000, Alexey Kardashevskiy wrote: > >>> It actually can change dynamically on x86 due to acpi interrupt links >>> which allow the guest a generic way to select from a set of possible >>> interrupt routing schemes. And of course a chipset driver could twiddle >>> bits if it wanted as well. So, we really do need the update notifiers >>> from my tree that this patch drops. >> >> >> You mean notifiers like these: ioapic_add_gsi_eoi_notifier? >> I did not drop them, we need them so I implemented them for XICS interrupt controller. > > So I haven't completely understood the problem, however: > > .../... > >> So it stores global IRQs in the config space but it really unclear who writes these _global_ numbers >> there. Is it the guest who allocates IRQs and writes the numbers into the config space so QEMU knows >> what pin is what IRQ? If so, I am wrong, you are right :) > > So you can certainly not write our global irq numbers in the config > space, since the config space IRQ_LINE register is only 8 bits long > which means it's not long enough. [had a char] No, it is all about piix3 extended capability. -- Alexey From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:50508) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUrZF-0005Mq-L3 for qemu-devel@nongnu.org; Wed, 16 May 2012 23:39:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SUrZE-0007Pf-03 for qemu-devel@nongnu.org; Wed, 16 May 2012 23:39:57 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:44534) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUrZD-0007PS-Py for qemu-devel@nongnu.org; Wed, 16 May 2012 23:39:55 -0400 Received: by dadv2 with SMTP id v2so2363796dad.4 for ; Wed, 16 May 2012 20:39:53 -0700 (PDT) Message-ID: <4FB47301.4060609@ozlabs.ru> Date: Thu, 17 May 2012 13:39:45 +1000 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <4FAE1171.1010806@ozlabs.ru> <20120514015830.GC30229@truffala.fritz.box> <4FB08867.9070103@ozlabs.ru> <1337200755.6954.269.camel@bling.home> <4FB45F8F.5000708@ozlabs.ru> <1337223641.30558.40.camel@pasglop> In-Reply-To: <1337223641.30558.40.camel@pasglop> Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH] qemu spapr-pci: added IRQ list to PCIBus List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: qemu-devel@nongnu.org, Alex Williamson , Alex Graf , anthony@codemonkey.ws, kvm@vger.kernel.org On 17/05/12 13:00, Benjamin Herrenschmidt wrote: > On Thu, 2012-05-17 at 12:16 +1000, Alexey Kardashevskiy wrote: > >>> It actually can change dynamically on x86 due to acpi interrupt links >>> which allow the guest a generic way to select from a set of possible >>> interrupt routing schemes. And of course a chipset driver could twiddle >>> bits if it wanted as well. So, we really do need the update notifiers >>> from my tree that this patch drops. >> >> >> You mean notifiers like these: ioapic_add_gsi_eoi_notifier? >> I did not drop them, we need them so I implemented them for XICS interrupt controller. > > So I haven't completely understood the problem, however: > > .../... > >> So it stores global IRQs in the config space but it really unclear who writes these _global_ numbers >> there. Is it the guest who allocates IRQs and writes the numbers into the config space so QEMU knows >> what pin is what IRQ? If so, I am wrong, you are right :) > > So you can certainly not write our global irq numbers in the config > space, since the config space IRQ_LINE register is only 8 bits long > which means it's not long enough. [had a char] No, it is all about piix3 extended capability. -- Alexey