From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Wang Subject: [PATCH] amd iommu: re-enable iommu msi if dom0 disabled it Date: Fri, 8 Jun 2012 15:28:02 +0200 Message-ID: <4FD1FDE2.5010907@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------000709040604060600000200" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich , Keir Fraser , "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org --------------000709040604060600000200 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: quoted-printable Hi Jan, I found that recent dom0 (e.g 3.4 pv_ops) disables iommu msi capability=20 for some reasons and iommu cannot generate any interrupts in this case. Attached patch re-enables it in device assignment. Thanks, Wei -- Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim, Landkreis M=FCnchen Registergericht M=FCnchen, HRB Nr. 43632 WEEE Registrierungsnummer 129 19551 Gesch=E4ftsf=FChrer: Alberto Bozzo --------------000709040604060600000200 Content-Type: text/x-patch; name="iommu-msi.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="iommu-msi.patch" Content-Description: iommu-msi.patch # HG changeset patch # Parent f6bfaf9daa508c31b2bca0e461202db2759426fc # User Wei Wang Re-enable iommu msi capability block if it is disabled by dom0 Signed-off-by: Wei Wang diff -r f6bfaf9daa50 xen/drivers/passthrough/amd/pci_amd_iommu.c --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Jun 06 16:37:05 2012 +0100 +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Fri Jun 08 15:13:11 2012 +0200 @@ -81,6 +81,30 @@ static void disable_translation(u32 *dte dte[0] = entry; } +static void iommu_msi_check_enable(struct amd_iommu *iommu) +{ + unsigned long flags; + uint16_t control; + uint8_t bus = PCI_BUS(iommu->bdf); + uint8_t dev = PCI_SLOT(iommu->bdf); + uint8_t func = PCI_FUNC(iommu->bdf); + + ASSERT( iommu->msi_cap ); + + spin_lock_irqsave(&iommu->lock, flags); + + control = pci_conf_read16(iommu->seg, bus, dev, func, + iommu->msi_cap + PCI_MSI_FLAGS); + if ( !(control & IOMMU_CONTROL_ENABLED) ) + { + control |= IOMMU_CONTROL_ENABLED; + pci_conf_write16(iommu->seg, bus, dev, func, + iommu->msi_cap + PCI_MSI_FLAGS, control); + } + + spin_unlock_irqrestore(&iommu->lock, flags); +} + static void amd_iommu_setup_domain_device( struct domain *domain, struct amd_iommu *iommu, int bdf) { @@ -101,6 +125,12 @@ static void amd_iommu_setup_domain_devic if ( ats_enabled ) dte_i = 1; + /* + * In some cases, dom0 disables iommu msi capability, + * re-enable it here. + */ + iommu_msi_check_enable(iommu); + /* get device-table entry */ req_id = get_dma_requestor_id(iommu->seg, bdf); dte = iommu->dev_table.buffer + (req_id * IOMMU_DEV_TABLE_ENTRY_SIZE); --------------000709040604060600000200 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --------------000709040604060600000200--