From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Wang Subject: Re: [PATCH] amd iommu: re-enable iommu msi if dom0 disabled it Date: Fri, 8 Jun 2012 15:41:00 +0200 Message-ID: <4FD200EC.6050005@amd.com> References: <4FD1FDE2.5010907@amd.com> <4FD1FEC8.5000708@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <4FD1FEC8.5000708@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Andrew Cooper Cc: "xen-devel@lists.xensource.com" , "Keir (Xen.org)" , Jan Beulich List-Id: xen-devel@lists.xenproject.org On 06/08/2012 03:31 PM, Andrew Cooper wrote: > On 08/06/12 14:28, Wei Wang wrote: >> Hi Jan, >> I found that recent dom0 (e.g 3.4 pv_ops) disables iommu msi capability >> for some reasons and iommu cannot generate any interrupts in this case. >> Attached patch re-enables it in device assignment. > > Under which circumstances should dom0 able to play with the IOMMUs ? > Surely the fact that dom0 can play with the IOMMUs is a bug in itself. It looks like some generic msi/pci codes disable it, not the Linux iommu = driver itself, which is only loaded on bare metal. AMD IOMMU expose = interrupt capability as a normal msi block. So the general pci/msi layer = of dom0 might touch it... Thanks, Wei >> >> Thanks, >> Wei >> >> -- >> Advanced Micro Devices GmbH >> Sitz: Dornach, Gemeinde Aschheim, >> Landkreis M=FCnchen Registergericht M=FCnchen, >> HRB Nr. 43632 WEEE Registrierungsnummer 129 19551 >> Gesch=E4ftsf=FChrer: >> Alberto Bozzo >