From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SmQxd-0000Wz-D2 for qemu-devel@nongnu.org; Wed, 04 Jul 2012 10:53:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SmQxa-0007Rd-UK for qemu-devel@nongnu.org; Wed, 04 Jul 2012 10:53:44 -0400 Received: from plane.gmane.org ([80.91.229.3]:35678) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SmQxa-0007Qq-Oe for qemu-devel@nongnu.org; Wed, 04 Jul 2012 10:53:42 -0400 Received: from list by plane.gmane.org with local (Exim 4.69) (envelope-from ) id 1SmQxZ-0005R2-5A for qemu-devel@nongnu.org; Wed, 04 Jul 2012 16:53:41 +0200 Received: from 213.33.220.118 ([213.33.220.118]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 04 Jul 2012 16:53:41 +0200 Received: from m.kozlov by 213.33.220.118 with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 04 Jul 2012 16:53:41 +0200 From: Maksim Kozlov Date: Wed, 04 Jul 2012 18:53:29 +0400 Message-ID: <4FF458E9.8010107@samsung.com> References: <1341393721-3606-1-git-send-email-m.kozlov@samsung.com> <1341393721-3606-2-git-send-email-m.kozlov@samsung.com> <4FF448F0.4050809@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v3 1/2] ARM: exynos4210: CMU support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, kyungmin.park@samsung.com 04.07.2012 18:14, Dunrong Huang пишет: >> >>>> + >>>> +static void exynos4210_cmu_set_pll(void *opaque, Exynos4210ClockState >>>> *pll) >>>> +{ >>>> + Exynos4210CmuState *s = opaque; >>>> + Exynos4210ClockState *source; >>>> + target_phys_addr_t offset = pll->div_reg; >>>> + ClockChangeEntry *cce; >>>> + uint32_t pdiv, mdiv, sdiv, enable; >>>> + >>>> + source = exynos4210_clock_find(pll->src_id); >>>> + >>>> + if (source == NULL) { >>>> + hw_error("We haven't find source clock %d (requested for %s)\n", >>>> + pll->src_id, pll->name); >>>> + } >>>> + >>>> + /* >>>> + * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1)) >>>> + */ >>>> + >>>> + enable = (s->reg[I_(offset)]& PLL_ENABLE_MASK)>> PLL_ENABLE_SHIFT; >>>> + mdiv = (s->reg[I_(offset)]& PLL_MDIV_MASK)>> PLL_MDIV_SHIFT; >>>> + pdiv = (s->reg[I_(offset)]& PLL_PDIV_MASK)>> PLL_PDIV_SHIFT; >>>> + sdiv = (s->reg[I_(offset)]& PLL_SDIV_MASK)>> PLL_SDIV_SHIFT; >>>> + >>>> + if (source) { >>>> + if (enable) { >>>> + pll->rate = mdiv * source->rate / (pdiv * (1<< (sdiv-1))); >>>> + } else { >>>> + pll->rate = 0; >>>> + } >>>> + } else { >>>> + hw_error("%s: Source undefined for %s\n", __func__, pll->name); >>>> + } >>>> + >>>> + QTAILQ_FOREACH(cce,&pll->clock_change_handler, entry) { >>>> >>>> + cce->func(cce->opaque); >>>> + } >>>> + >>>> + PRINT_DEBUG("%s rate: %llu\n", pll->name, pll->rate); >>> >>> pll->rate is of type uint64_t incompatible with "%llu" >> >> >> Type uint64_t is included from /usr/include/stdint.h as >> >> typedef unsigned long long int uint64_t; > From /usr/include/stdint.h ,the uint64_t is defined by: > #if __WORDSIZE == 64 > typedef unsigned long int uint64_t; > #else > __extension__ > typedef unsigned long long int uint64_t; > #endif > On my machine(64 bit), there will be a incompatibility error. Yes, I have understood now. I don't use neither 64 bit system nor compiler and have not ever faced with this problem. Thanks for remarks > > As Peter said, you should use PRIu64 instead of llu >> >> and 'll' specifies that a following 'u' conversion specifier applies to a >> unsigned long long argument >> >> Why do you think they incompatible? >> >> >> -- >> MK > > >