Re: [PATCH] Xen/MCE: adjust for future new vMCE model

[Christoph Egger <Christoph.Egger@amd.com>]

On 07/05/12 11:36, Liu, Jinsong wrote:

> Christoph Egger wrote:
>> On 07/05/12 09:00, Jan Beulich wrote:
>>
>>>>>> On 04.07.12 at 18:08, "Liu, Jinsong" <jinsong.liu@intel.com>
>>>>>> wrote: Christoph Egger wrote: On 07/04/12 15:08, Liu, Jinsong
>>>>>> wrote: +    g_mcg_cap = MCG_TES_P | MCG_SER_P | GUEST_BANK_NUM; +
>>>>>
>>>>>
>>>>> Is MCG_TES_P and MCG_SER_P emulated independent if the host has
>>>>> them or not? For AMD this only works if the answer is yes.
>>>>>
>>>>> (I know in upstream this code path is used by Intel only but I have
>>>>> patches that brings this code path in use by both AMD and Intel.)
>>>>>
>>>>> Christoph
>>>>
>>>> I'm not sure if AMD has these 2 bits in MCG_CAP. Could you tell me
>>>> where can I get AMD's *latest* open doc (something like amd
>>>> architecture programmer manual)? 
>>>>
>>>> If AMD has these 2 bits, it's safe to set them independent of host
>>>> capability -- guest will just think it running on a platform w/
>>>> some events *possilbe* (though actually may never occur),
>>>> hypervisor know what actually occur and has the flexibility to
>>>> decide what it would like to inject to guest.
>>>
>>> According to the latest doc I have access to, neither of these two
>>> bits are known there (nor are any other of the bits beyond 8). But
>>> as we don't want to surface model specific behavior to guests,
>>> having these bits set seems the right thing in any case. The
>>> MCi_STATUS values reported to guests just may need some
>>> additional massaging.
>>>
>>> All this is of course assuming that AMD won't assign these bits
>>> _different_ meanings in the future, but as that would be pretty
>>> counter productive (requiring more vendor specific code in all OSes)
>>> that seems pretty unlikely. Christoph?
>>
>> Let me ask back internally.
>>
>> Christoph
> 
> Christoph, where can I get more AMD mce details (of course open doc)?

> I read 'amd64 architecture programmer manual (v2).pdf' (publication
> number 24593, Rev 3.18, May 2011), but seems it's quite general. Per
> that document I cannot answer some of your questions. Are there more
> deatials in K7/K8/K10 docs (but I fail to find these docs)?





Public documentation is available at
http://developer.amd.com/documentation/guides/Pages/default.aspx

The latest APM v2 you are asking is
http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf

CPU family specific information are in the BKDG
(BIOS and Kernel Developer Guide).

K8 documentation is no longer available. The only difference to
Family10h is that Family10h has three exra MC4 MISC  MSRs.

Christoph


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