From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53283) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Smm1I-00039g-6P for qemu-devel@nongnu.org; Thu, 05 Jul 2012 09:23:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Smm16-0000yY-OZ for qemu-devel@nongnu.org; Thu, 05 Jul 2012 09:22:55 -0400 Received: from cantor2.suse.de ([195.135.220.15]:40047 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Smm16-0000xx-7N for qemu-devel@nongnu.org; Thu, 05 Jul 2012 09:22:44 -0400 Message-ID: <4FF5951F.9060502@suse.de> Date: Thu, 05 Jul 2012 15:22:39 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1341110730-444-1-git-send-email-proljc@gmail.com> <1341110730-444-2-git-send-email-proljc@gmail.com> In-Reply-To: <1341110730-444-2-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v8 01/16] target-or32: Add target stubs and QOM cpu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jia Liu Cc: Paolo Bonzini , qemu-devel@nongnu.org, Juan Quintela Am 01.07.2012 04:45, schrieb Jia Liu: > Add OpenRISC target stubs and cpu support. >=20 > Signed-off-by: Jia Liu > --- > arch_init.c | 2 + > arch_init.h | 1 + > configure | 14 +- > cpu-exec.c | 2 + > default-configs/or32-softmmu.mak | 4 + > elf.h | 2 + > hw/openrisc/Makefile.objs | 1 + > poison.h | 1 + > target-openrisc/Makefile.objs | 3 + > target-openrisc/cpu.c | 236 ++++++++++++++++++++++++++++++= + > target-openrisc/cpu.h | 286 ++++++++++++++++++++++++++++++= ++++++++ > target-openrisc/intrpt.c | 30 ++++ > target-openrisc/machine.c | 30 ++++ > target-openrisc/mmu.c | 39 ++++++ > target-openrisc/mmu_helper.c | 43 ++++++ > target-openrisc/translate.c | 75 ++++++++++ > 16 files changed, 767 insertions(+), 2 deletions(-) > create mode 100644 default-configs/or32-softmmu.mak > create mode 100644 hw/openrisc/Makefile.objs > create mode 100644 target-openrisc/Makefile.objs > create mode 100644 target-openrisc/cpu.c > create mode 100644 target-openrisc/cpu.h > create mode 100644 target-openrisc/intrpt.c > create mode 100644 target-openrisc/machine.c > create mode 100644 target-openrisc/mmu.c > create mode 100644 target-openrisc/mmu_helper.c > create mode 100644 target-openrisc/translate.c > diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.o= bjs > new file mode 100644 > index 0000000..21b76b2 > --- /dev/null > +++ b/target-openrisc/Makefile.objs > @@ -0,0 +1,3 @@ > +obj-$(CONFIG_SOFTMMU) +=3D machine.o > +obj-y +=3D cpu.o intrpt.o mmu.o translate.o intrpt.o? Any chance of a better to read/remember file name? > +obj-y +=3D mmu_helper.o > diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c > new file mode 100644 > index 0000000..64ddc98 > --- /dev/null > +++ b/target-openrisc/cpu.c > @@ -0,0 +1,236 @@ > +/* > + * QEMU OpenRISC CPU > + * > + * Copyright (c) 2012 Jia Liu Two-space indentation? (also in other files) > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "cpu.h" > +#include "qemu-common.h" > +#ifndef CONFIG_USER_ONLY > +#include "hw/loader.h" > +#endif Not yet needed in this patch? > + > +/* CPUClass::reset() */ > +static void openrisc_cpu_reset(CPUState *s) > +{ > + OpenRISCCPU *cpu =3D OPENRISC_CPU(s); > + OpenRISCCPUClass *occ =3D OPENRISC_CPU_GET_CLASS(cpu); > + > + if (qemu_loglevel_mask(CPU_LOG_RESET)) { > + qemu_log("CPU Reset (CPU %d)\n", cpu->env.cpu_index); > + log_cpu_state(&cpu->env, 0); > + } > + > + occ->parent_reset(s); > + > + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); Note, if you wanted, you could've declared a CPUOpenRISCState *env to avoid re-typing "cpu->env." or "&cpu->env". > + > + tlb_flush(&cpu->env, 1); > + /*tb_flush(&cpu->env); FIXME: Do we need it? */ > + > + cpu->env.pc =3D 0x100; > + cpu->env.sr =3D SR_FO | SR_SM; > + cpu->env.exception_index =3D -1; > + > + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; > + cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S; > + cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & = (6 << 2)); > + cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & = (6 << 2)); > + > +#ifndef CONFIG_USER_ONLY > + cpu->env.picmr =3D 0x00000000; > + cpu->env.picsr =3D 0x00000000; > + > + cpu->env.ttmr =3D 0x00000000; > + cpu->env.ttcr =3D 0x00000000; > +#endif > +} > + > +static inline int openrisc_feature(OpenRISCCPU *cpu, int feature) This could return bool. > +{ > + return (cpu->env.feature & (1u << feature)) !=3D 0; > +} > + > +static inline void set_feature(OpenRISCCPU *cpu, int feature) > +{ > + cpu->env.feature |=3D 1u << feature; > +} > + > +void openrisc_cpu_realize(Object *obj, Error **errp) > +{ > + OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); > + if (openrisc_feature(cpu, OPENRISC_FEATURE_OR1200)) { > + set_feature(cpu, OPENRISC_FEATURE_OB32S); > + set_feature(cpu, OPENRISC_FEATURE_OF32S); > + } > + > + qemu_init_vcpu(&cpu->env); > +} > + > +static void openrisc_cpu_initfn(Object *obj) > +{ > + OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); > + cpu_exec_init(&cpu->env); > +} > + > +/* CPU models */ > +static void or1200_initfn(Object *obj) > +{ > + OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); > + > + set_feature(cpu, OPENRISC_FEATURE_OR1200); > + > + cpu_reset(CPU(cpu)); > +} > + > +static void openrisc_any_initfn(Object *obj) > +{ > + OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); > + > + set_feature(cpu, OPENRISC_FEATURE_OB32S); > + set_feature(cpu, OPENRISC_FEATURE_OF32S); > + > + cpu_reset(CPU(cpu)); > +} Paolo, could class_base_init or something help with this pattern of needing to do something in every derived initfn? On the other hand I think we should move cpu_reset() into the realizefn instead, that would avoid this issue here. > + > +typedef struct OpenRISCCPUInfo { > + const char *name; > + void (*initfn)(Object *obj); > +} OpenRISCCPUInfo; > + > +static const OpenRISCCPUInfo openrisc_cpus[] =3D { > + { .name =3D "or1200", .initfn =3D or1200_initfn }, > + { .name =3D "any", .initfn =3D openrisc_any_initfn }, > +}; > + > +static void openrisc_cpu_class_init(ObjectClass *oc, void *data) > +{ > + OpenRISCCPUClass *occ =3D OPENRISC_CPU_CLASS(oc); > + CPUClass *cc =3D CPU_CLASS(occ); > + > + occ->parent_reset =3D cc->reset; > + cc->reset =3D openrisc_cpu_reset; > +} > + > +static void cpu_register(const OpenRISCCPUInfo *info) > +{ > + TypeInfo type_info =3D { > + .name =3D info->name, > + .parent =3D TYPE_OPENRISC_CPU, > + .instance_size =3D sizeof(OpenRISCCPU), > + .instance_init =3D info->initfn, > + .class_size =3D sizeof(OpenRISCCPUClass), > + }; > + > + type_register_static(&type_info); > +} > + > +static const TypeInfo openrisc_cpu_type_info =3D { > + .name =3D TYPE_OPENRISC_CPU, > + .parent =3D TYPE_CPU, > + .instance_size =3D sizeof(OpenRISCCPU), > + .instance_init =3D openrisc_cpu_initfn, > + .abstract =3D false, > + .class_size =3D sizeof(OpenRISCCPUClass), > + .class_init =3D openrisc_cpu_class_init, > +}; > + > +static void openrisc_cpu_register_types(void) > +{ > + int i; > + > + type_register_static(&openrisc_cpu_type_info); > + for (i =3D 0; i < ARRAY_SIZE(openrisc_cpus); i++) { > + cpu_register(&openrisc_cpus[i]); > + } > +} > + > +OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) > +{ > + OpenRISCCPU *cpu; > + static int inited; > + inited =3D 0; > + > + if (!object_class_by_name(cpu_model)) { > + return NULL; > + } > + cpu =3D OPENRISC_CPU(object_new(cpu_model)); This currently does a reset in initfn. > + cpu->env.cpu_model_str =3D cpu_model; > + > + openrisc_cpu_realize(OBJECT(cpu), NULL); > + > +#ifndef CONFIG_USER_ONLY > + cpu_openrisc_mmu_init(cpu); > +#endif > + > + if (tcg_enabled() && !inited) { > + inited =3D 1; > + openrisc_translate_init(); > + } Could you move this into the initfn please like Igor has done for x86? > + > + cpu_reset(CPU(cpu)); It is then reset again here, which is why I think doing it once in the realizefn would be sufficient. > + > + return cpu; > +} > + > +typedef struct OpenRISCCPUList { > + fprintf_function cpu_fprintf; > + FILE *file; > +} OpenRISCCPUList; > + > +/* Sort alphabetically by type name, except for "any". */ > +static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b= ) > +{ > + ObjectClass *class_a =3D (ObjectClass *)a; > + ObjectClass *class_b =3D (ObjectClass *)b; > + const char *name_a, *name_b; > + > + name_a =3D object_class_get_name(class_a); > + name_b =3D object_class_get_name(class_b); > + if (strcmp(name_a, "any") =3D=3D 0) { > + return 1; > + } else if (strcmp(name_b, "any") =3D=3D 0) { > + return -1; > + } else { > + return strcmp(name_a, name_b); > + } > +} > + > +static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) > +{ > + ObjectClass *oc =3D data; > + OpenRISCCPUList *s =3D user_data; > + > + (*s->cpu_fprintf)(s->file, " %s\n", > + object_class_get_name(oc)); > +} > + > +void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) > +{ > + OpenRISCCPUList s =3D { > + .file =3D f, > + .cpu_fprintf =3D cpu_fprintf, > + }; > + GSList *list; > + > + list =3D object_class_get_list(TYPE_OPENRISC_CPU, false); > + list =3D g_slist_sort(list, openrisc_cpu_list_compare); > + (*cpu_fprintf)(f, "Available CPUs:\n"); > + g_slist_foreach(list, openrisc_cpu_list_entry, &s); > + g_slist_free(list); > +} > + > +type_init(openrisc_cpu_register_types) > diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h > new file mode 100644 > index 0000000..728e4b3 > --- /dev/null > +++ b/target-openrisc/cpu.h > @@ -0,0 +1,286 @@ > +/* > + * OpenRISC virtual CPU header. > + * > + * Copyright (c) 2011-2012 Jia Liu > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#ifndef CPU_OPENRISC_H > +#define CPU_OPENRISC_H > + > +#if defined(TARGET_OPENRISC64) > +#define TARGET_LONG_BITS 64 > +#define ELF_MACHINE EM_NONE I don't see any provisions in configure for openrisc64? > +#else > +#define TARGET_LONG_BITS 32 > +#define ELF_MACHINE EM_OPENRISC > +#endif > + > +#define CPUArchState struct CPUOpenRISCState > + > +#include "config.h" > +#include "qemu-common.h" > +#include "cpu-defs.h" > +#include "softfloat.h" > +#include "qemu/cpu.h" > +#include "error.h" > + > +#define TYPE_OPENRISC_CPU "or32-cpu" "openrisc-cpu"? Also for or64 it should be adjusted. > + > +#define OPENRISC_CPU_CLASS(klass) \ > + OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU) > +#define OPENRISC_CPU(obj) \ > + OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU) > +#define OPENRISC_CPU_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU) > + > +/** > + * OpenRISCCPUClass: > + * @parent_reset: The parent class' reset handler. > + * > + * A OpenRISC CPU model. > + */ > +typedef struct OpenRISCCPUClass { > + /*< private >*/ > + CPUClass parent_class; > + /*< public >*/ > + > + void (*parent_reset)(CPUState *cpu); > +} OpenRISCCPUClass; > + > +#define NB_MMU_MODES 3 > + > +#define TARGET_PAGE_BITS 13 > + > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > +/* Internal flags, delay slot flag */ > +#define D_FLAG 1 > + > +/* Registers */ > +enum { > + R0 =3D 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, > + R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, > + R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, > + R31 > +}; > + > +/* Register aliases */ > +enum { > + R_ZERO =3D R0, > + R_SP =3D R1, > + R_FP =3D R2, > + R_LR =3D R9, > + R_RV =3D R11, > + R_RVH =3D R12 > +}; > + > +/* Unit presece register */ > +enum { > + UPR_UP =3D (1 << 0), > + UPR_DCP =3D (1 << 1), > + UPR_ICP =3D (1 << 2), > + UPR_DMP =3D (1 << 3), > + UPR_IMP =3D (1 << 4), > + UPR_MP =3D (1 << 5), > + UPR_DUP =3D (1 << 6), > + UPR_PCUR =3D (1 << 7), > + UPR_PMP =3D (1 << 8), > + UPR_PICP =3D (1 << 9), > + UPR_TTP =3D (1 << 10), > + UPR_CUP =3D (255 << 24), > +}; > + > +/* CPU configure register */ > +enum { > + CPUCFGR_NSGF =3D (15 << 0), > + CPUCFGR_CGF =3D (1 << 4), > + CPUCFGR_OB32S =3D (1 << 5), > + CPUCFGR_OB64S =3D (1 << 6), > + CPUCFGR_OF32S =3D (1 << 7), > + CPUCFGR_OF64S =3D (1 << 8), > + CPUCFGR_OV64S =3D (1 << 9), > +}; > + > +/* DMMU configure register */ > +enum { > + DMMUCFGR_NTW =3D (3 << 0), > + DMMUCFGR_NTS =3D (7 << 2), > + DMMUCFGR_NAE =3D (7 << 5), > + DMMUCFGR_CRI =3D (1 << 8), > + DMMUCFGR_PRI =3D (1 << 9), > + DMMUCFGR_TEIRI =3D (1 << 10), > + DMMUCFGR_HTR =3D (1 << 11), > +}; > + > +/* IMMU configure register */ > +enum { > + IMMUCFGR_NTW =3D (3 << 0), > + IMMUCFGR_NTS =3D (7 << 2), > + IMMUCFGR_NAE =3D (7 << 5), > + IMMUCFGR_CRI =3D (1 << 8), > + IMMUCFGR_PRI =3D (1 << 9), > + IMMUCFGR_TEIRI =3D (1 << 10), > + IMMUCFGR_HTR =3D (1 << 11), > +}; > + > +/* Supervisor register */ > +enum { > + SR_SM =3D (1 << 0), > + SR_TEE =3D (1 << 1), > + SR_IEE =3D (1 << 2), > + SR_DCE =3D (1 << 3), > + SR_ICE =3D (1 << 4), > + SR_DME =3D (1 << 5), > + SR_IME =3D (1 << 6), > + SR_LEE =3D (1 << 7), > + SR_CE =3D (1 << 8), > + SR_F =3D (1 << 9), > + SR_CY =3D (1 << 10), > + SR_OV =3D (1 << 11), > + SR_OVE =3D (1 << 12), > + SR_DSX =3D (1 << 13), > + SR_EPH =3D (1 << 14), > + SR_FO =3D (1 << 15), > + SR_SUMRA =3D (1 << 16), > + SR_SCE =3D (1 << 17), > +}; > + > +/* OpenRISC Hardware Capabilities */ > +enum { > + OPENRISC_FEATURE_NSGF, > + OPENRISC_FEATURE_CGF, > + OPENRISC_FEATURE_OB32S, > + OPENRISC_FEATURE_OB64S, > + OPENRISC_FEATURE_OF32S, > + OPENRISC_FEATURE_OF64S, > + OPENRISC_FEATURE_OV64S, > + OPENRISC_FEATURE_OR1200, > +}; > + > +typedef struct CPUOpenRISCState { > + target_ulong gpr[32]; /* General registers */ > + target_ulong pc; /* Program counter */ > + target_ulong npc; /* Next PC */ > + target_ulong ppc; /* Prev PC */ > + target_ulong jmp_pc; /* Jump PC */ > + > + uint32_t sr; /* Supervisor register */ > + uint32_t vr; /* Version register */ > + uint32_t upr; /* Unit presence register */ > + uint32_t cpucfgr; /* CPU configure register */ > + uint32_t dmmucfgr; /* DMMU configure register */ > + uint32_t immucfgr; /* IMMU configure register */ > + > + uint32_t flags; /* cpu_flags, we only use it for excepti= on > + in solt so far. */ > + uint32_t btaken; /* the SR_F bit */ > + > + CPU_COMMON > + > +#ifndef CONFIG_USER_ONLY > + struct QEMUTimer *timer; > + uint32_t ttmr; /* Timer tick mode register */ > + uint32_t ttcr; /* Timer tick count register */ > + > + uint32_t picmr; /* Interrupt mask register */ > + uint32_t picsr; /* Interrupt contrl register*/ > +#endif > + uint32_t feature; /* CPU Capabilities */ Could the feature(s) field be moved into OpenRISCCPU after env? > +} CPUOpenRISCState; > + > +/** > + * OpenRISCCPU: > + * @env: #CPUOpenRISCState > + * > + * A OpenRISC CPU. > + */ > +typedef struct OpenRISCCPU { > + /*< private >*/ > + CPUState parent_obj; > + /*< public >*/ > + > + CPUOpenRISCState env; > +} OpenRISCCPU; > + > +static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) > +{ > + return OPENRISC_CPU(container_of(env, OpenRISCCPU, env)); > +} > + > +#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) > + > +OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); > +void openrisc_cpu_realize(Object *obj, Error **errp); > + > +void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); > +int cpu_openrisc_exec(CPUOpenRISCState *s); > +void do_interrupt(CPUOpenRISCState *env); > +void openrisc_translate_init(void); > + > +#define cpu_list cpu_openrisc_list > +#define cpu_exec cpu_openrisc_exec > +#define cpu_gen_code cpu_openrisc_gen_code > + > +#define CPU_SAVE_VERSION 1 Is this still needed? > + > +#ifndef CONFIG_USER_ONLY > +void cpu_openrisc_mmu_init(OpenRISCCPU *cpu); > +#endif > + > +static inline CPUOpenRISCState *cpu_init(const char *cpu_model) > +{ > + OpenRISCCPU *cpu =3D cpu_openrisc_init(cpu_model); > + if (cpu) { > + return &cpu->env; > + } > + return NULL; > +} > + > +#include "cpu-all.h" > + > +static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, > + target_ulong *pc, > + target_ulong *cs_base, int *fl= ags) > +{ > + *pc =3D env->pc; > + *cs_base =3D 0; > + *flags =3D 0; > +} > + > +static inline int cpu_mmu_index(CPUOpenRISCState *env) > +{ > + return 0; > +} > + > +static inline bool cpu_has_work(CPUOpenRISCState *env) > +{ > + return true; > +} > + > +#include "exec-all.h" > + > +static inline target_ulong cpu_get_pc(CPUOpenRISCState *env) > +{ > + return env->pc; > +} > + > +static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBl= ock *tb) > +{ > + env->pc =3D tb->pc; > +} > + > +#endif /* CPU_OPENRISC_H */ > diff --git a/target-openrisc/intrpt.c b/target-openrisc/intrpt.c > new file mode 100644 > index 0000000..a3bb7f8 > --- /dev/null > +++ b/target-openrisc/intrpt.c > @@ -0,0 +1,30 @@ > +/* > + * OpenRISC interrupt. > + * > + * Copyright (c) 2011-2012 Jia Liu > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "cpu.h" > +#include "qemu-common.h" > +#include "gdbstub.h" > +#include "host-utils.h" > +#ifndef CONFIG_USER_ONLY > +#include "hw/loader.h" > +#endif > + > +void do_interrupt(CPUOpenRISCState *env) > +{ > +} > diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c > new file mode 100644 > index 0000000..11bf275 > --- /dev/null > +++ b/target-openrisc/machine.c > @@ -0,0 +1,30 @@ > +/* > + * OpenRISC Machine > + * > + * Copyright (c) 2011-2012 Jia Liu > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "hw/hw.h" > +#include "hw/boards.h" > + > +void cpu_save(QEMUFile *f, void *opaque) > +{ > +} > + > +int cpu_load(QEMUFile *f, void *opaque, int version_id) > +{ > + return 0; > +} [snip] Shouldn't this be using VMState? Was there any problem converting? Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg