From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Egger Subject: Re: [PATCH] Xen/MCE: adjust for future new vMCE model Date: Fri, 6 Jul 2012 11:12:59 +0200 Message-ID: <4FF6AC1B.4070601@amd.com> References: <4FF4444D.5040304@amd.com> <3908561D78D1C84285E8C5FCA982C28F1934524A@ORSMSX104.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "Liu, Jinsong" Cc: "Luck, Tony" , Keir Fraser , Ian Campbell , "Jiang, Yunhong" , "Auld, Will" , "xen-devel@lists.xensource.com" , Jan Beulich List-Id: xen-devel@lists.xenproject.org On 07/05/12 20:38, Liu, Jinsong wrote: > Luck, Tony wrote: >>> I'm not sure if AMD has these 2 bits in MCG_CAP. Could you tell me >>> where can I get >>> AMD's *latest* open doc (something like amd architecture programmer >>> manual)? >>> >>> If AMD has these 2 bits, it's safe to set them independent of host >>> capability -- guest >>> will just think it running on a platform w/ some events *possilbe* >>> (though actually >>> may never occur), hypervisor know what actually occur and has the >>> flexibility to >>> decide what it would like to inject to guest. >>> >>> This code is only used by Intel, and it's only for not blocking >>> future vMCE, so it just do minimal necessary update. >> >> I think you should be very wary of creating "Franken-machines" that >> look half AMD (according to CPUID) and half Intel (according to >> MCG_CAP). You can look at the Linux code and check whether we always >> make sensible decisions when presented with >> such a system ... but you may not have that luxury with other guest >> operating systems. My general mantra is that untested code paths have >> bugs. >> >> -Tony > > Yes, I indeed concern AMD cpuid vs. Intel MCG_CAP. Do you suggest > that we'd better separately provide Intel's and AMD's vMCE interface? That is no reason to have seperate vmce_intel.c and vmce_amd.c files. >>From the last patch in function vmce_init_msr(): + g_mcg_cap = MCG_TES_P | MCG_SER_P | GUEST_BANK_NUM; + I think, this should be changed to: g_mcg_cap = GUEST_BANK_NUM; if (cpu_vendor == X86_VENDOR_INTEL) g_mcg_cap |= MCG_TES_P | MCG_SER_P; Another question: What happens when a guest access the MSRs 0xc0000408, 0xc0000409 and 0xc000040a ? Christoph -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85689 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632