Re: [PATCH V2 5/5] perf/x86: Add Intel Nehalem-EX uncore support

["Yan, Zheng" <zheng.z.yan@intel.com>]

On 07/10/2012 08:17 PM, Peter Zijlstra wrote:
> On Thu, 2012-07-05 at 14:32 +0800, Yan, Zheng wrote:
>> The uncore subsystem in Nehalem-EX consists of 7 components
>> (U-Box, C-Box, B-Box, S-Box, R-Box, M-Box and W-Box). This
>> patch is large because the way to program these boxes is
>> diverse.
>>
> Thanks, I added the below little delta.
> 
> Did you manage to fix that SNB-EP crash already?

Yes, commit 42089697 (perf/x86: Detect number of instances of uncore CBox)
should fix that.

> 
> Also, should we be adding 58 (IVB) to the SNB uncore? The SDM states it
> should all be the same programming wise.
> 

It's completely untested, I think it's better not to do that now.

> ---
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> 
> @@ -893,7 +893,7 @@ static struct attribute_group nhmex_unco
>  static struct intel_uncore_type nhmex_uncore_cbox = {
>  	.name			= "cbox",
>  	.num_counters		= 6,
> -	.num_boxes		= 8,
> +	.num_boxes		= 10,
>  	.perf_ctr_bits		= 48,
>  	.event_ctl		= NHMEX_C0_MSR_PMON_EV_SEL0,
>  	.perf_ctr		= NHMEX_C0_MSR_PMON_CTR0,

This doesn't work. The MSRs for Cbox 8/9 in WSM-EX aren't contiguous with
Cbox 0~7. Furthermore the encoding for the FVC register in the Mbox are
different between NHM-EX and WSM-EX.

Please don't merge this patch, I will send a new one with WSM-EX support
and some fixes soon.

Regards
Yan, Zheng