diff for duplicates of <4FFE7979.4060000@googlemail.com> diff --git a/a/1.txt b/N1/1.txt index 379268d..98064e0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -14,10 +14,10 @@ Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Mike Turquette <mturquette@ti.com> -Cc: devicetree-discuss at lists.ozlabs.org -Cc: linux-doc at vger.kernel.org -Cc: linux-kernel at vger.kernel.org -Cc: linux-arm-kernel at lists.infradead.org +Cc: devicetree-discuss@lists.ozlabs.org +Cc: linux-doc@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Cc: linux-arm-kernel@lists.infradead.org --- .../bindings/clock/clock-gating-control.txt | 80 +++++++++++++++++++ drivers/clk/clk-gate.c | 84 ++++++++++++++++++++ @@ -86,7 +86,7 @@ index 0000000..05f5728 + }; + + /* register-based clock gating control */ -+ gating-control at f10d0038 { ++ gating-control@f10d0038 { + compatible = "clock-gating-control"; + reg = <0xf10d0038 0x4>; + clocks = <&osc>; @@ -95,19 +95,19 @@ index 0000000..05f5728 + #size-cells = <0>; + + /* USB0 clock gate on register bit 0 with inverted polarity */ -+ cg_usb0: clockgate at 0 { ++ cg_usb0: clockgate@0 { + reg = <0 1>; /* register bit 0, inverted polarity */ + }; + + /* PCIe0 clock gate on register bit 1 with normal polarity + * and named output clock */ -+ cg_pcie0: clockgate at 1 { ++ cg_pcie0: clockgate@1 { + reg = <1 0>; /* register bit 1, normal polarity */ + clock-output-names = "pcie0_clk"; + }; + + /* SATA clock gate with different parent clock */ -+ cg_sata: clockgate at 3 { ++ cg_sata: clockgate@3 { + reg = <3 0>; /* register bit 3, normal polarity */ + clocks = <&sata_clk>; + }; @@ -223,8 +223,3 @@ index b97f61e..499eac2 100644 * -- 1.7.10 - --------------- next part -------------- -An embedded and charset-unspecified text was scrubbed... -Name: Attached Message Part -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20120712/397fe449/attachment.ksh> diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..d9ba19d --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,5 @@ +Content-Type: text/plain; + name="Attached Message Part" +Content-Transfer-Encoding: 7bit +Content-Disposition: attachment; + filename="Attached Message Part" diff --git a/N1/2.txt b/N1/2.txt new file mode 100644 index 0000000..bd4bcf2 --- /dev/null +++ b/N1/2.txt @@ -0,0 +1,224 @@ +This patch adds support for using clock gates (clk-gate) from DT based +on Rob Herrings DT clk binding support for 3.6. + +It adds a helper function to clk-gate to allocate all resources required by +a set of individual clock gates, i.e. register base address and lock. Each +clock gate is described as a child of the clock-gating-control in DT and +also created by the helper function. + +Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com> +Cc: Grant Likely <grant.likely@secretlab.ca> +Cc: Rob Herring <rob.herring@calxeda.com> +Cc: Rob Landley <rob@landley.net> +Cc: Mike Turquette <mturquette@ti.com> +Cc: devicetree-discuss@lists.ozlabs.org +Cc: linux-doc@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Cc: linux-arm-kernel@lists.infradead.org +--- + .../bindings/clock/clock-gating-control.txt | 80 +++++++++++++++++++ + drivers/clk/clk-gate.c | 84 ++++++++++++++++++++ + include/linux/clk-provider.h | 2 + + 3 files changed, 166 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/clock-gating-control.txt + +diff --git a/Documentation/devicetree/bindings/clock/clock-gating-control.txt b/Documentation/devicetree/bindings/clock/clock-gating-control.txt +new file mode 100644 +index 0000000..05f5728 +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/clock-gating-control.txt +@@ -0,0 +1,80 @@ ++Binding for simple clock gating control based on clock gate register with one ++bit per clock gate. This is a clock consumer and also a clock provider for a ++set of gated clocks that are described as children of this node. Each clock gate ++is described by a bit number and polarity to control the gate. ++ ++This binding uses the common clock binding[1]. ++ ++[1] Documentation/devicetree/bindings/clock/clock-bindings.txt ++ ++==Clock gating control== ++ ++Required properties: ++- compatible : shall be "clock-gating-control". ++- reg : should contain the register physical address and length for ++ the clock gating control. ++- clocks : shared parent clock for all gated clocks. ++- #clock-cells : from common clock binding; shall be set to 0. ++- #address-cells : number of cells required to describe a clock gate; ++ should be <2>. ++- #size-cells : should be zero. ++ ++Each individual clock gate bit is described as a child of the ++corresponding gating control register with the following properties. ++ ++Required child properties: ++- reg : should contain the individual bit and polarity to control ++ the clock gate. A polarity of 0 means that by setting the ++ bit to 1 the clock passes through the clock gate while ++ setting the bit to 0 disables the clock. Any other value ++ for polarity inverts the meaning of the control bit. ++ ++Optional child properties: ++- clocks : overrides the shared parent clock for this clock gate ++ by the clock passed in this property. ++- clock-output-names : from common clock binding; allows to set ++ a specific name for the gated clock output. ++ ++==Example== ++ ++ /* fixed root clock */ ++ osc: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <166666667>; ++ }; ++ ++ /* sata peripheral clock */ ++ sata_clk: ext-oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <25000000>; ++ }; ++ ++ /* register-based clock gating control */ ++ gating-control@f10d0038 { ++ compatible = "clock-gating-control"; ++ reg = <0xf10d0038 0x4>; ++ clocks = <&osc>; ++ #clock-cells = <0>; ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ /* USB0 clock gate on register bit 0 with inverted polarity */ ++ cg_usb0: clockgate@0 { ++ reg = <0 1>; /* register bit 0, inverted polarity */ ++ }; ++ ++ /* PCIe0 clock gate on register bit 1 with normal polarity ++ * and named output clock */ ++ cg_pcie0: clockgate@1 { ++ reg = <1 0>; /* register bit 1, normal polarity */ ++ clock-output-names = "pcie0_clk"; ++ }; ++ ++ /* SATA clock gate with different parent clock */ ++ cg_sata: clockgate@3 { ++ reg = <3 0>; /* register bit 3, normal polarity */ ++ clocks = <&sata_clk>; ++ }; ++ }; +diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c +index 578465e..1e88907 100644 +--- a/drivers/clk/clk-gate.c ++++ b/drivers/clk/clk-gate.c +@@ -15,6 +15,9 @@ + #include <linux/io.h> + #include <linux/err.h> + #include <linux/string.h> ++#include <linux/of.h> ++#include <linux/of_address.h> ++#include <linux/of_platform.h> + + /** + * DOC: basic gatable clock which can gate and ungate it's ouput +@@ -148,3 +151,84 @@ struct clk *clk_register_gate(struct device *dev, const char *name, + + return clk; + } ++ ++#ifdef CONFIG_OF ++/** ++ * of_clock_gating_control_setup() - Setup function for clock gate control ++ * This is a helper for using clk-gate from OF device tree. It allocates ++ * a common lock for a base register and creates the individual clk-gates. ++ */ ++void __init of_clock_gating_control_setup(struct device_node *np) ++{ ++ struct device_node *child; ++ const char *pclk_name; ++ void __iomem *base; ++ spinlock_t *lockp; ++ unsigned int rnum; ++ u64 addr; ++ ++ pclk_name = of_clk_get_parent_name(np, 0); ++ if (!pclk_name) { ++ pr_debug("%s: unable to get parent clock for %s\n", ++ __func__, np->full_name); ++ return; ++ } ++ ++ lockp = kzalloc(sizeof(spinlock_t), GFP_KERNEL); ++ if (!lockp) { ++ pr_debug("%s: unable to allocate spinlock for %s\n", ++ __func__, np->full_name); ++ return; ++ } ++ ++ spin_lock_init(lockp); ++ base = of_iomap(np, 0); ++ rnum = sizeof(resource_size_t) * 8; ++ addr = of_translate_address(np, of_get_property(np, "reg", NULL)); ++ ++ pr_debug("create clock gate control %s\n", np->full_name); ++ ++ for_each_child_of_node(np, child) { ++ struct clk *cg; ++ const char *cg_name; ++ const char *cg_pclk_name; ++ u32 propval[2]; ++ unsigned int rbit; ++ ++ if (of_property_read_u32_array(child, "reg", propval, 2)) { ++ pr_debug("%s: wrong #reg on %s\n", ++ __func__, child->full_name); ++ continue; ++ } ++ ++ rbit = propval[0]; ++ if (rbit >= rnum) { ++ pr_debug("%s: bit position of %s exceeds resources\n", ++ __func__, child->full_name); ++ continue; ++ } ++ ++ cg_pclk_name = of_clk_get_parent_name(child, 0); ++ if (!pclk_name) ++ cg_pclk_name = pclk_name; ++ ++ if (of_property_read_string(child, "clock-output-names", ++ &cg_name)) { ++ unsigned int nlen = 4 + 16 + strlen(child->name); ++ char *name = kzalloc(nlen+1, GFP_KERNEL); ++ if (!name) ++ continue; ++ snprintf(name, nlen, "%u@%llx.%s", rbit, ++ (unsigned long long)addr, child->name); ++ cg_name = name; ++ } ++ ++ pr_debug(" create clock gate: %s\n", cg_name); ++ ++ cg = clk_register_gate(NULL, cg_name, cg_pclk_name, 0, ++ base, rbit, propval[1], lockp); ++ if (cg) ++ of_clk_add_provider(child, of_clk_src_simple_get, cg); ++ } ++} ++#endif +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index b97f61e..499eac2 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -205,6 +205,8 @@ struct clk *clk_register_gate(struct device *dev, const char *name, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); + ++void of_clock_gating_control_setup(struct device_node *np); ++ + /** + * struct clk_divider - adjustable divider clock + * +-- +1.7.10 diff --git a/a/content_digest b/N1/content_digest index f8d854b..00243fe 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,16 @@ - "From\0sebastian.hesselbarth@googlemail.com (Sebastian Hesselbarth)\0" + "From\0Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>\0" "Subject\0[RESEND PATCH 1/1] clk: add DT support for clock gating control\0" "Date\0Thu, 12 Jul 2012 09:15:05 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Grant Likely <grant.likely@secretlab.ca>\0" + "Cc\0Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>" + Rob Herring <rob.herring@calxeda.com> + Rob Landley <rob@landley.net> + Mike Turquette <mturquette@ti.com> + devicetree-discuss@lists.ozlabs.org + linux-doc@vger.kernel.org + linux-kernel@vger.kernel.org + " linux-arm-kernel@lists.infradead.org\0" + "\01:1\0" "b\0" "As Rob's clock binding support patch is now up on clk-next, I'd like to\n" "draw attention on this patch again.\n" @@ -20,10 +28,10 @@ "Cc: Rob Herring <rob.herring@calxeda.com>\n" "Cc: Rob Landley <rob@landley.net>\n" "Cc: Mike Turquette <mturquette@ti.com>\n" - "Cc: devicetree-discuss at lists.ozlabs.org\n" - "Cc: linux-doc at vger.kernel.org\n" - "Cc: linux-kernel at vger.kernel.org\n" - "Cc: linux-arm-kernel at lists.infradead.org\n" + "Cc: devicetree-discuss@lists.ozlabs.org\n" + "Cc: linux-doc@vger.kernel.org\n" + "Cc: linux-kernel@vger.kernel.org\n" + "Cc: linux-arm-kernel@lists.infradead.org\n" "---\n" " .../bindings/clock/clock-gating-control.txt | 80 +++++++++++++++++++\n" " drivers/clk/clk-gate.c | 84 ++++++++++++++++++++\n" @@ -92,7 +100,7 @@ "+\t};\n" "+\n" "+\t/* register-based clock gating control */\n" - "+\tgating-control at f10d0038 {\n" + "+\tgating-control@f10d0038 {\n" "+\t\tcompatible = \"clock-gating-control\";\n" "+\t\treg = <0xf10d0038 0x4>;\n" "+\t\tclocks = <&osc>;\n" @@ -101,19 +109,19 @@ "+\t\t#size-cells = <0>;\n" "+\n" "+\t\t/* USB0 clock gate on register bit 0 with inverted polarity */\n" - "+\t\tcg_usb0: clockgate at 0 {\n" + "+\t\tcg_usb0: clockgate@0 {\n" "+\t\t\treg = <0 1>; /* register bit 0, inverted polarity */\n" "+\t\t};\n" "+\n" "+\t\t/* PCIe0 clock gate on register bit 1 with normal polarity\n" "+\t\t * and named output clock */\n" - "+\t\tcg_pcie0: clockgate at 1 {\n" + "+\t\tcg_pcie0: clockgate@1 {\n" "+\t\t\treg = <1 0>; /* register bit 1, normal polarity */\n" "+\t\t\tclock-output-names = \"pcie0_clk\";\n" "+\t\t};\n" "+\n" "+\t\t/* SATA clock gate with different parent clock */\n" - "+\t\tcg_sata: clockgate at 3 {\n" + "+\t\tcg_sata: clockgate@3 {\n" "+\t\t\treg = <3 0>; /* register bit 3, normal polarity */\n" "+\t\t\tclocks = <&sata_clk>;\n" "+\t\t};\n" @@ -228,11 +236,233 @@ " * struct clk_divider - adjustable divider clock\n" " *\n" "-- \n" - "1.7.10\n" + 1.7.10 + "\01:2\0" + "fn\0Attached Message Part\0" + "b\0" + "This patch adds support for using clock gates (clk-gate) from DT based\n" + "on Rob Herrings DT clk binding support for 3.6.\n" "\n" - "-------------- next part --------------\n" - "An embedded and charset-unspecified text was scrubbed...\n" - "Name: Attached Message Part\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20120712/397fe449/attachment.ksh> + "It adds a helper function to clk-gate to allocate all resources required by\n" + "a set of individual clock gates, i.e. register base address and lock. Each\n" + "clock gate is described as a child of the clock-gating-control in DT and\n" + "also created by the helper function.\n" + "\n" + "Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>\n" + "Cc: Grant Likely <grant.likely@secretlab.ca>\n" + "Cc: Rob Herring <rob.herring@calxeda.com>\n" + "Cc: Rob Landley <rob@landley.net>\n" + "Cc: Mike Turquette <mturquette@ti.com>\n" + "Cc: devicetree-discuss@lists.ozlabs.org\n" + "Cc: linux-doc@vger.kernel.org\n" + "Cc: linux-kernel@vger.kernel.org\n" + "Cc: linux-arm-kernel@lists.infradead.org\n" + "---\n" + " .../bindings/clock/clock-gating-control.txt | 80 +++++++++++++++++++\n" + " drivers/clk/clk-gate.c | 84 ++++++++++++++++++++\n" + " include/linux/clk-provider.h | 2 +\n" + " 3 files changed, 166 insertions(+)\n" + " create mode 100644 Documentation/devicetree/bindings/clock/clock-gating-control.txt\n" + "\n" + "diff --git a/Documentation/devicetree/bindings/clock/clock-gating-control.txt b/Documentation/devicetree/bindings/clock/clock-gating-control.txt\n" + "new file mode 100644\n" + "index 0000000..05f5728\n" + "--- /dev/null\n" + "+++ b/Documentation/devicetree/bindings/clock/clock-gating-control.txt\n" + "@@ -0,0 +1,80 @@\n" + "+Binding for simple clock gating control based on clock gate register with one\n" + "+bit per clock gate. This is a clock consumer and also a clock provider for a\n" + "+set of gated clocks that are described as children of this node. Each clock gate\n" + "+is described by a bit number and polarity to control the gate.\n" + "+\n" + "+This binding uses the common clock binding[1].\n" + "+\n" + "+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt\n" + "+\n" + "+==Clock gating control==\n" + "+\n" + "+Required properties:\n" + "+- compatible : shall be \"clock-gating-control\".\n" + "+- reg : should contain the register physical address and length for\n" + "+ the clock gating control.\n" + "+- clocks : shared parent clock for all gated clocks.\n" + "+- #clock-cells : from common clock binding; shall be set to 0.\n" + "+- #address-cells : number of cells required to describe a clock gate;\n" + "+ should be <2>.\n" + "+- #size-cells : should be zero.\n" + "+\n" + "+Each individual clock gate bit is described as a child of the\n" + "+corresponding gating control register with the following properties.\n" + "+\n" + "+Required child properties:\n" + "+- reg : should contain the individual bit and polarity to control\n" + "+ the clock gate. A polarity of 0 means that by setting the\n" + "+ bit to 1 the clock passes through the clock gate while\n" + "+\tsetting the bit to 0 disables the clock. Any other value\n" + "+ \tfor polarity inverts the meaning of the control bit.\n" + "+\n" + "+Optional child properties:\n" + "+- clocks : overrides the shared parent clock for this clock gate\n" + "+ by the clock passed in this property.\n" + "+- clock-output-names : from common clock binding; allows to set\n" + "+ a specific name for the gated clock output.\n" + "+\n" + "+==Example==\n" + "+\n" + "+\t/* fixed root clock */\n" + "+\tosc: oscillator {\n" + "+\t\tcompatible = \"fixed-clock\";\n" + "+\t\t#clock-cells = <0>;\n" + "+\t\tclock-frequency = <166666667>;\n" + "+\t};\n" + "+\n" + "+\t/* sata peripheral clock */\n" + "+\tsata_clk: ext-oscillator {\n" + "+\t\tcompatible = \"fixed-clock\";\n" + "+\t\t#clock-cells = <0>;\n" + "+\t\tclock-frequency = <25000000>;\n" + "+\t};\n" + "+\n" + "+\t/* register-based clock gating control */\n" + "+\tgating-control@f10d0038 {\n" + "+\t\tcompatible = \"clock-gating-control\";\n" + "+\t\treg = <0xf10d0038 0x4>;\n" + "+\t\tclocks = <&osc>;\n" + "+\t\t#clock-cells = <0>;\n" + "+\t\t#address-cells = <2>;\n" + "+\t\t#size-cells = <0>;\n" + "+\n" + "+\t\t/* USB0 clock gate on register bit 0 with inverted polarity */\n" + "+\t\tcg_usb0: clockgate@0 {\n" + "+\t\t\treg = <0 1>; /* register bit 0, inverted polarity */\n" + "+\t\t};\n" + "+\n" + "+\t\t/* PCIe0 clock gate on register bit 1 with normal polarity\n" + "+\t\t * and named output clock */\n" + "+\t\tcg_pcie0: clockgate@1 {\n" + "+\t\t\treg = <1 0>; /* register bit 1, normal polarity */\n" + "+\t\t\tclock-output-names = \"pcie0_clk\";\n" + "+\t\t};\n" + "+\n" + "+\t\t/* SATA clock gate with different parent clock */\n" + "+\t\tcg_sata: clockgate@3 {\n" + "+\t\t\treg = <3 0>; /* register bit 3, normal polarity */\n" + "+\t\t\tclocks = <&sata_clk>;\n" + "+\t\t};\n" + "+\t};\n" + "diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c\n" + "index 578465e..1e88907 100644\n" + "--- a/drivers/clk/clk-gate.c\n" + "+++ b/drivers/clk/clk-gate.c\n" + "@@ -15,6 +15,9 @@\n" + " #include <linux/io.h>\n" + " #include <linux/err.h>\n" + " #include <linux/string.h>\n" + "+#include <linux/of.h>\n" + "+#include <linux/of_address.h>\n" + "+#include <linux/of_platform.h>\n" + " \n" + " /**\n" + " * DOC: basic gatable clock which can gate and ungate it's ouput\n" + "@@ -148,3 +151,84 @@ struct clk *clk_register_gate(struct device *dev, const char *name,\n" + " \n" + " \treturn clk;\n" + " }\n" + "+\n" + "+#ifdef CONFIG_OF\n" + "+/**\n" + "+ * of_clock_gating_control_setup() - Setup function for clock gate control\n" + "+ * This is a helper for using clk-gate from OF device tree. It allocates\n" + "+ * a common lock for a base register and creates the individual clk-gates.\n" + "+ */\n" + "+void __init of_clock_gating_control_setup(struct device_node *np)\n" + "+{\n" + "+\tstruct device_node *child;\n" + "+\tconst char *pclk_name;\n" + "+\tvoid __iomem *base;\n" + "+\tspinlock_t *lockp;\n" + "+\tunsigned int rnum;\n" + "+\tu64 addr;\n" + "+\n" + "+\tpclk_name = of_clk_get_parent_name(np, 0);\n" + "+\tif (!pclk_name) {\n" + "+\t\tpr_debug(\"%s: unable to get parent clock for %s\\n\",\n" + "+\t\t\t__func__, np->full_name);\n" + "+\t\treturn;\n" + "+\t}\n" + "+\n" + "+\tlockp = kzalloc(sizeof(spinlock_t), GFP_KERNEL);\n" + "+\tif (!lockp) {\n" + "+\t\tpr_debug(\"%s: unable to allocate spinlock for %s\\n\",\n" + "+\t\t\t __func__, np->full_name);\n" + "+\t\treturn;\n" + "+\t}\n" + "+\n" + "+\tspin_lock_init(lockp);\n" + "+\tbase = of_iomap(np, 0);\n" + "+\trnum = sizeof(resource_size_t) * 8;\n" + "+\taddr = of_translate_address(np, of_get_property(np, \"reg\", NULL));\n" + "+\n" + "+\tpr_debug(\"create clock gate control %s\\n\", np->full_name);\n" + "+\n" + "+\tfor_each_child_of_node(np, child) {\n" + "+\t\tstruct clk *cg;\n" + "+\t\tconst char *cg_name;\n" + "+\t\tconst char *cg_pclk_name;\n" + "+\t\tu32 propval[2];\n" + "+\t\tunsigned int rbit;\n" + "+\n" + "+\t\tif (of_property_read_u32_array(child, \"reg\", propval, 2)) {\n" + "+\t\t\tpr_debug(\"%s: wrong #reg on %s\\n\",\n" + "+\t\t\t\t __func__, child->full_name);\n" + "+\t\t\tcontinue;\n" + "+\t\t}\n" + "+\n" + "+\t\trbit = propval[0];\n" + "+\t\tif (rbit >= rnum) {\n" + "+\t\t\tpr_debug(\"%s: bit position of %s exceeds resources\\n\",\n" + "+\t\t\t\t __func__, child->full_name);\n" + "+\t\t\tcontinue;\n" + "+\t\t}\n" + "+\n" + "+\t\tcg_pclk_name = of_clk_get_parent_name(child, 0);\n" + "+\t\tif (!pclk_name)\n" + "+\t\t\tcg_pclk_name = pclk_name;\n" + "+\n" + "+\t\tif (of_property_read_string(child, \"clock-output-names\",\n" + "+\t\t\t\t\t &cg_name)) {\n" + "+\t\t\tunsigned int nlen = 4 + 16 + strlen(child->name);\n" + "+\t\t\tchar *name = kzalloc(nlen+1, GFP_KERNEL);\n" + "+\t\t\tif (!name)\n" + "+\t\t\t\tcontinue;\n" + "+\t\t\tsnprintf(name, nlen, \"%u@%llx.%s\", rbit,\n" + "+\t\t\t\t (unsigned long long)addr, child->name);\n" + "+\t\t\tcg_name = name;\n" + "+\t\t}\n" + "+\n" + "+\t\tpr_debug(\" create clock gate: %s\\n\", cg_name);\n" + "+\n" + "+\t\tcg = clk_register_gate(NULL, cg_name, cg_pclk_name, 0,\n" + "+\t\t\t\t base, rbit, propval[1], lockp);\n" + "+\t\tif (cg)\n" + "+\t\t\tof_clk_add_provider(child, of_clk_src_simple_get, cg);\n" + "+\t}\n" + "+}\n" + "+#endif\n" + "diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h\n" + "index b97f61e..499eac2 100644\n" + "--- a/include/linux/clk-provider.h\n" + "+++ b/include/linux/clk-provider.h\n" + "@@ -205,6 +205,8 @@ struct clk *clk_register_gate(struct device *dev, const char *name,\n" + " \t\tvoid __iomem *reg, u8 bit_idx,\n" + " \t\tu8 clk_gate_flags, spinlock_t *lock);\n" + " \n" + "+void of_clock_gating_control_setup(struct device_node *np);\n" + "+\n" + " /**\n" + " * struct clk_divider - adjustable divider clock\n" + " *\n" + "-- \n" + 1.7.10 -7204de9850d5298608ca4af6cc224015078f08d9121f7911c697a2411969beb5 +5a23da14e1b0fd4ed90ad6dea169c82a4aa171e010a77d7b9cd8932a7f243ab0
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