diff for duplicates of <4FFEBF8A.1020700@gmail.com> diff --git a/a/1.txt b/N1/1.txt index ebaa876..02bcdc0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -15,10 +15,10 @@ On 07/12/2012 02:15 AM, Sebastian Hesselbarth wrote: > Cc: Rob Herring <rob.herring@calxeda.com> > Cc: Rob Landley <rob@landley.net> > Cc: Mike Turquette <mturquette@ti.com> -> Cc: devicetree-discuss at lists.ozlabs.org -> Cc: linux-doc at vger.kernel.org -> Cc: linux-kernel at vger.kernel.org -> Cc: linux-arm-kernel at lists.infradead.org +> Cc: devicetree-discuss@lists.ozlabs.org +> Cc: linux-doc@vger.kernel.org +> Cc: linux-kernel@vger.kernel.org +> Cc: linux-arm-kernel@lists.infradead.org > --- > .../bindings/clock/clock-gating-control.txt | 80 > +++++++++++++++++++ @@ -97,7 +97,7 @@ This is a bit of overloading reg to specify the polarity. > + }; > + > + /* register-based clock gating control */ -> + gating-control at f10d0038 { +> + gating-control@f10d0038 { > + compatible = "clock-gating-control"; > + reg = <0xf10d0038 0x4>; > + clocks = <&osc>; @@ -106,19 +106,19 @@ This is a bit of overloading reg to specify the polarity. > + #size-cells = <0>; > + > + /* USB0 clock gate on register bit 0 with inverted polarity */ -> + cg_usb0: clockgate at 0 { +> + cg_usb0: clockgate@0 { > + reg = <0 1>; /* register bit 0, inverted polarity */ > + }; > + > + /* PCIe0 clock gate on register bit 1 with normal polarity > + * and named output clock */ -> + cg_pcie0: clockgate at 1 { +> + cg_pcie0: clockgate@1 { > + reg = <1 0>; /* register bit 1, normal polarity */ > + clock-output-names = "pcie0_clk"; > + }; > + > + /* SATA clock gate with different parent clock */ -> + cg_sata: clockgate at 3 { +> + cg_sata: clockgate@3 { > + reg = <3 0>; /* register bit 3, normal polarity */ > + clocks = <&sata_clk>; > + }; diff --git a/a/content_digest b/N1/content_digest index 0598e47..e73d07e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,15 @@ "ref\04FFE7979.4060000@googlemail.com\0" - "From\0robherring2@gmail.com (Rob Herring)\0" - "Subject\0[RESEND PATCH 1/1] clk: add DT support for clock gating control\0" + "From\0Rob Herring <robherring2@gmail.com>\0" + "Subject\0Re: [RESEND PATCH 1/1] clk: add DT support for clock gating control\0" "Date\0Thu, 12 Jul 2012 07:14:02 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>\0" + "Cc\0Grant Likely <grant.likely@secretlab.ca>" + Rob Landley <rob@landley.net> + Mike Turquette <mturquette@ti.com> + devicetree-discuss@lists.ozlabs.org + linux-doc@vger.kernel.org + linux-kernel@vger.kernel.org + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 07/12/2012 02:15 AM, Sebastian Hesselbarth wrote:\n" @@ -22,10 +29,10 @@ "> Cc: Rob Herring <rob.herring@calxeda.com>\n" "> Cc: Rob Landley <rob@landley.net>\n" "> Cc: Mike Turquette <mturquette@ti.com>\n" - "> Cc: devicetree-discuss at lists.ozlabs.org\n" - "> Cc: linux-doc at vger.kernel.org\n" - "> Cc: linux-kernel at vger.kernel.org\n" - "> Cc: linux-arm-kernel at lists.infradead.org\n" + "> Cc: devicetree-discuss@lists.ozlabs.org\n" + "> Cc: linux-doc@vger.kernel.org\n" + "> Cc: linux-kernel@vger.kernel.org\n" + "> Cc: linux-arm-kernel@lists.infradead.org\n" "> ---\n" "> .../bindings/clock/clock-gating-control.txt | 80\n" "> +++++++++++++++++++\n" @@ -104,7 +111,7 @@ "> + };\n" "> +\n" "> + /* register-based clock gating control */\n" - "> + gating-control at f10d0038 {\n" + "> + gating-control@f10d0038 {\n" "> + compatible = \"clock-gating-control\";\n" "> + reg = <0xf10d0038 0x4>;\n" "> + clocks = <&osc>;\n" @@ -113,19 +120,19 @@ "> + #size-cells = <0>;\n" "> +\n" "> + /* USB0 clock gate on register bit 0 with inverted polarity */\n" - "> + cg_usb0: clockgate at 0 {\n" + "> + cg_usb0: clockgate@0 {\n" "> + reg = <0 1>; /* register bit 0, inverted polarity */\n" "> + };\n" "> +\n" "> + /* PCIe0 clock gate on register bit 1 with normal polarity\n" "> + * and named output clock */\n" - "> + cg_pcie0: clockgate at 1 {\n" + "> + cg_pcie0: clockgate@1 {\n" "> + reg = <1 0>; /* register bit 1, normal polarity */\n" "> + clock-output-names = \"pcie0_clk\";\n" "> + };\n" "> +\n" "> + /* SATA clock gate with different parent clock */\n" - "> + cg_sata: clockgate at 3 {\n" + "> + cg_sata: clockgate@3 {\n" "> + reg = <3 0>; /* register bit 3, normal polarity */\n" "> + clocks = <&sata_clk>;\n" "> + };\n" @@ -252,4 +259,4 @@ "> * struct clk_divider - adjustable divider clock\n" > * -8f2fb1b2d2c42d61bcfbfb33eec89e10f161b24195ce894ec1f37acb0942ef22 +5db8f3c11e43c906919bc103ea46d6e7aa1b82c2645b20735c6079aa0998f7bc
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