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([2a02:a449:4071:0:32d0:42ff:fe10:6983]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-be9d63c1792sm254186766b.49.2026.05.31.14.03.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 May 2026 14:03:26 -0700 (PDT) Message-ID: <4a201f58-11ba-4e3b-980c-00eae365e956@gmail.com> Date: Sun, 31 May 2026 23:03:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Johan Jonker Subject: [PATCH v3 07/12] rockchip: reset: make reset-rockchip available in SPL To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, trini@konsulko.com, hl@rock-chips.com, jernej.skrabec@gmail.com, w.egorov@phytec.de, jagan@amarulasolutions.com, heiko@sntech.de, jonas@kwiboo.se, michael@amarulasolutions.com, lukma@denx.de, marex@denx.de, u-boot@lists.denx.de, upstream@lists.phytec.de References: <3a63b606-621d-486c-9aae-3a819ef05430@gmail.com> Content-Language: en-US, ar-EG In-Reply-To: <3a63b606-621d-486c-9aae-3a819ef05430@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Make reset-rockchip available for use with dwc2 phy in SPL to load U-boot (full) from a USB disk. Signed-off-by: Johan Jonker --- drivers/reset/Kconfig | 9 +++++++++ drivers/reset/Makefile | 4 ++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 66911199c8ba..10aa1ee9598b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -100,6 +100,15 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config SPL_RESET_ROCKCHIP + bool "Reset controller driver for Rockchip SoCs in SPL" + depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK + default n + help + Support for reset controller on rockchip SoC. The main limitation + though is that some reset signals, like I2C or MISC reset multiple + devices. + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on DM_RESET && TARGET_HSDK diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 088545c64733..afb54b24ac95 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2016, NVIDIA CORPORATION. # -obj-$(CONFIG_DM_RESET) += reset-uclass.o +obj-$(CONFIG_$(PHASE_)DM_RESET) += reset-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o obj-$(CONFIG_STI_RESET) += sti-reset.o @@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o +obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o -- 2.39.5