From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chao Du Date: Tue, 20 Feb 2024 10:58:25 +0800 (GMT+08:00) Subject: [PATCH v1 1/3] RISC-V: KVM: Implement kvm_arch_vcpu_ioctl_set_guest_debug() In-Reply-To: References: <20240206074931.22930-1-duchao@eswincomputing.com> <20240206074931.22930-2-duchao@eswincomputing.com> Message-ID: <4a5a30cd.18c.18dc4734699.Coremail.duchao@eswincomputing.com> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On 2024-02-14 21:19, Anup Patel wrote: > > On Tue, Feb 6, 2024 at 1:22?PM Chao Du wrote: > > > > kvm_vm_ioctl_check_extension(): Return 1 if KVM_CAP_SET_GUEST_DEBUG is > > being checked. > > > > kvm_arch_vcpu_ioctl_set_guest_debug(): Update the guest_debug flags > > from userspace accordingly. Route the breakpoint exceptions to HS mode > > if the VM is being debugged by userspace, by clearing the corresponding > > bit in hedeleg CSR. > > > > Signed-off-by: Chao Du > > --- > > arch/riscv/include/uapi/asm/kvm.h | 1 + > > arch/riscv/kvm/vcpu.c | 15 +++++++++++++-- > > arch/riscv/kvm/vm.c | 1 + > > 3 files changed, 15 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > > index d6b7a5b95874..8890977836f0 100644 > > --- a/arch/riscv/include/uapi/asm/kvm.h > > +++ b/arch/riscv/include/uapi/asm/kvm.h > > @@ -17,6 +17,7 @@ > > > > #define __KVM_HAVE_IRQ_LINE > > #define __KVM_HAVE_READONLY_MEM > > +#define __KVM_HAVE_GUEST_DEBUG > > > > #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 > > > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > > index b5ca9f2e98ac..6cee974592ac 100644 > > --- a/arch/riscv/kvm/vcpu.c > > +++ b/arch/riscv/kvm/vcpu.c > > @@ -475,8 +475,19 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, > > int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, > > struct kvm_guest_debug *dbg) > > { > > - /* TODO; To be implemented later. */ > > - return -EINVAL; > > + if (dbg->control & KVM_GUESTDBG_ENABLE) { > > + if (vcpu->guest_debug != dbg->control) { > > + vcpu->guest_debug = dbg->control; > > + csr_clear(CSR_HEDELEG, BIT(EXC_BREAKPOINT)); > > + } > > + } else { > > + if (vcpu->guest_debug != 0) { > > + vcpu->guest_debug = 0; > > + csr_set(CSR_HEDELEG, BIT(EXC_BREAKPOINT)); > > + } > > + } > > This is broken because directly setting breakpoint exception delegation > in CSR also affects other VCPUs running on the same host CPU. > > To address the above, we should do the following: > 1) Add "unsigned long hedeleg" in "struct kvm_vcpu_config" which > is pre-initialized in kvm_riscv_vcpu_setup_config() without setting > EXC_BREAKPOINT bit. > 2) The kvm_arch_vcpu_ioctl_set_guest_debug() should only set/clear > EXC_BREAKPOINT bit in "hedeleg" of "struct kvm_vcpu_config". > 3) The kvm_riscv_vcpu_swap_in_guest_state() must write the > HEDELEG csr before entering the Guest/VM. > > Regards, > Anup > Thanks for the review and detailed suggestion. Maybe we could make it a bit easier: 1) The kvm_arch_vcpu_ioctl_set_guest_debug() only update vcpu->guest_debug accordingly. 2) The kvm_riscv_vcpu_swap_in_guest_state() check vcpu->guest_debug and set/clear the HEDELEG csr accordingly. Could you confirm if this is OK? If yes, I will post another revision. Regards, Chao > > + > > + return 0; > > } > > > > static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) > > diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c > > index ce58bc48e5b8..7396b8654f45 100644 > > --- a/arch/riscv/kvm/vm.c > > +++ b/arch/riscv/kvm/vm.c > > @@ -186,6 +186,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) > > case KVM_CAP_READONLY_MEM: > > case KVM_CAP_MP_STATE: > > case KVM_CAP_IMMEDIATE_EXIT: > > + case KVM_CAP_SET_GUEST_DEBUG: > > r = 1; > > break; > > case KVM_CAP_NR_VCPUS: > > -- > > 2.17.1 > > > > > > -- > > kvm-riscv mailing list > > kvm-riscv at lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 20A0E53368 for ; Tue, 20 Feb 2024 03:01:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from duchao$eswincomputing.com ( [10.64.113.11] ) by ajax-webmail-app2 (Coremail) ; Tue, 20 Feb 2024 10:58:25 +0800 (GMT+08:00) Date: Tue, 20 Feb 2024 10:58:25 +0800 (GMT+08:00) X-CM-HeaderCharset: UTF-8 From: "Chao Du" To: "Anup Patel" Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, anup@brainfault.org, atishp@atishpatra.org, pbonzini@redhat.com, shuah@kernel.org, dbarboza@ventanamicro.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, duchao713@qq.com Subject: Re: [PATCH v1 1/3] RISC-V: KVM: Implement kvm_arch_vcpu_ioctl_set_guest_debug() X-Priority: 3 X-Mailer: Coremail Webmail Server Version XT6.0.3 build 20220420(169d3f8c) Copyright (c) 2002-2024 www.mailtech.cn mispb-72143050-eaf5-4703-89e0-86624513b4ce-eswincomputing.com In-Reply-To: References: <20240206074931.22930-1-duchao@eswincomputing.com> <20240206074931.22930-2-duchao@eswincomputing.com> Content-Transfer-Encoding: base64 Content-Type: text/plain; charset=UTF-8 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <4a5a30cd.18c.18dc4734699.Coremail.duchao@eswincomputing.com> X-Coremail-Locale: en_US X-CM-TRANSID:TQJkCgA3xtRRFdRlabwQAA--.8582W X-CM-SenderInfo: xgxfxt3r6h245lqf0zpsxwx03jof0z/1tbiAgENDGXTdLMOzwAAsy X-Coremail-Antispam: 1Ur529EdanIXcx71UUUUU7IcSsGvfJ3iIAIbVAYjsxI4VWxJw CS07vEb4IE77IF4wCS07vE1I0E4x80FVAKz4kxMIAIbVAFxVCaYxvI4VCIwcAKzIAtYxBI daVFxhVjvjDU= T24gMjAyNC0wMi0xNCAyMToxOSwgQW51cCBQYXRlbCA8YXBhdGVsQHZlbnRhbmFtaWNyby5jb20+ IHdyb3RlOgo+IAo+IE9uIFR1ZSwgRmViIDYsIDIwMjQgYXQgMToyMuKAr1BNIENoYW8gRHUgPGR1 Y2hhb0Blc3dpbmNvbXB1dGluZy5jb20+IHdyb3RlOgo+ID4KPiA+IGt2bV92bV9pb2N0bF9jaGVj a19leHRlbnNpb24oKTogUmV0dXJuIDEgaWYgS1ZNX0NBUF9TRVRfR1VFU1RfREVCVUcgaXMKPiA+ IGJlaW5nIGNoZWNrZWQuCj4gPgo+ID4ga3ZtX2FyY2hfdmNwdV9pb2N0bF9zZXRfZ3Vlc3RfZGVi dWcoKTogVXBkYXRlIHRoZSBndWVzdF9kZWJ1ZyBmbGFncwo+ID4gZnJvbSB1c2Vyc3BhY2UgYWNj b3JkaW5nbHkuIFJvdXRlIHRoZSBicmVha3BvaW50IGV4Y2VwdGlvbnMgdG8gSFMgbW9kZQo+ID4g aWYgdGhlIFZNIGlzIGJlaW5nIGRlYnVnZ2VkIGJ5IHVzZXJzcGFjZSwgYnkgY2xlYXJpbmcgdGhl IGNvcnJlc3BvbmRpbmcKPiA+IGJpdCBpbiBoZWRlbGVnIENTUi4KPiA+Cj4gPiBTaWduZWQtb2Zm LWJ5OiBDaGFvIER1IDxkdWNoYW9AZXN3aW5jb21wdXRpbmcuY29tPgo+ID4gLS0tCj4gPiAgYXJj aC9yaXNjdi9pbmNsdWRlL3VhcGkvYXNtL2t2bS5oIHwgIDEgKwo+ID4gIGFyY2gvcmlzY3Yva3Zt L3ZjcHUuYyAgICAgICAgICAgICB8IDE1ICsrKysrKysrKysrKystLQo+ID4gIGFyY2gvcmlzY3Yv a3ZtL3ZtLmMgICAgICAgICAgICAgICB8ICAxICsKPiA+ICAzIGZpbGVzIGNoYW5nZWQsIDE1IGlu c2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCj4gPgo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvcmlz Y3YvaW5jbHVkZS91YXBpL2FzbS9rdm0uaCBiL2FyY2gvcmlzY3YvaW5jbHVkZS91YXBpL2FzbS9r dm0uaAo+ID4gaW5kZXggZDZiN2E1Yjk1ODc0Li44ODkwOTc3ODM2ZjAgMTAwNjQ0Cj4gPiAtLS0g YS9hcmNoL3Jpc2N2L2luY2x1ZGUvdWFwaS9hc20va3ZtLmgKPiA+ICsrKyBiL2FyY2gvcmlzY3Yv aW5jbHVkZS91YXBpL2FzbS9rdm0uaAo+ID4gQEAgLTE3LDYgKzE3LDcgQEAKPiA+Cj4gPiAgI2Rl ZmluZSBfX0tWTV9IQVZFX0lSUV9MSU5FCj4gPiAgI2RlZmluZSBfX0tWTV9IQVZFX1JFQURPTkxZ X01FTQo+ID4gKyNkZWZpbmUgX19LVk1fSEFWRV9HVUVTVF9ERUJVRwo+ID4KPiA+ICAjZGVmaW5l IEtWTV9DT0FMRVNDRURfTU1JT19QQUdFX09GRlNFVCAxCj4gPgo+ID4gZGlmZiAtLWdpdCBhL2Fy Y2gvcmlzY3Yva3ZtL3ZjcHUuYyBiL2FyY2gvcmlzY3Yva3ZtL3ZjcHUuYwo+ID4gaW5kZXggYjVj YTlmMmU5OGFjLi42Y2VlOTc0NTkyYWMgMTAwNjQ0Cj4gPiAtLS0gYS9hcmNoL3Jpc2N2L2t2bS92 Y3B1LmMKPiA+ICsrKyBiL2FyY2gvcmlzY3Yva3ZtL3ZjcHUuYwo+ID4gQEAgLTQ3NSw4ICs0NzUs MTkgQEAgaW50IGt2bV9hcmNoX3ZjcHVfaW9jdGxfc2V0X21wc3RhdGUoc3RydWN0IGt2bV92Y3B1 ICp2Y3B1LAo+ID4gIGludCBrdm1fYXJjaF92Y3B1X2lvY3RsX3NldF9ndWVzdF9kZWJ1ZyhzdHJ1 Y3Qga3ZtX3ZjcHUgKnZjcHUsCj4gPiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgc3RydWN0IGt2bV9ndWVzdF9kZWJ1ZyAqZGJnKQo+ID4gIHsKPiA+IC0gICAgICAgLyog VE9ETzsgVG8gYmUgaW1wbGVtZW50ZWQgbGF0ZXIuICovCj4gPiAtICAgICAgIHJldHVybiAtRUlO VkFMOwo+ID4gKyAgICAgICBpZiAoZGJnLT5jb250cm9sICYgS1ZNX0dVRVNUREJHX0VOQUJMRSkg ewo+ID4gKyAgICAgICAgICAgICAgIGlmICh2Y3B1LT5ndWVzdF9kZWJ1ZyAhPSBkYmctPmNvbnRy b2wpIHsKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIHZjcHUtPmd1ZXN0X2RlYnVnID0gZGJn LT5jb250cm9sOwo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgY3NyX2NsZWFyKENTUl9IRURF TEVHLCBCSVQoRVhDX0JSRUFLUE9JTlQpKTsKPiA+ICsgICAgICAgICAgICAgICB9Cj4gPiArICAg ICAgIH0gZWxzZSB7Cj4gPiArICAgICAgICAgICAgICAgaWYgKHZjcHUtPmd1ZXN0X2RlYnVnICE9 IDApIHsKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIHZjcHUtPmd1ZXN0X2RlYnVnID0gMDsK PiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGNzcl9zZXQoQ1NSX0hFREVMRUcsIEJJVChFWENf QlJFQUtQT0lOVCkpOwo+ID4gKyAgICAgICAgICAgICAgIH0KPiA+ICsgICAgICAgfQo+IAo+IFRo aXMgaXMgYnJva2VuIGJlY2F1c2UgZGlyZWN0bHkgc2V0dGluZyBicmVha3BvaW50IGV4Y2VwdGlv biBkZWxlZ2F0aW9uCj4gaW4gQ1NSIGFsc28gYWZmZWN0cyBvdGhlciBWQ1BVcyBydW5uaW5nIG9u IHRoZSBzYW1lIGhvc3QgQ1BVLgo+IAo+IFRvIGFkZHJlc3MgdGhlIGFib3ZlLCB3ZSBzaG91bGQg ZG8gdGhlIGZvbGxvd2luZzoKPiAxKSBBZGQgInVuc2lnbmVkIGxvbmcgaGVkZWxlZyIgaW4gInN0 cnVjdCBrdm1fdmNwdV9jb25maWciIHdoaWNoCj4gICAgaXMgcHJlLWluaXRpYWxpemVkIGluIGt2 bV9yaXNjdl92Y3B1X3NldHVwX2NvbmZpZygpIHdpdGhvdXQgc2V0dGluZwo+ICAgIEVYQ19CUkVB S1BPSU5UIGJpdC4KPiAyKSBUaGUga3ZtX2FyY2hfdmNwdV9pb2N0bF9zZXRfZ3Vlc3RfZGVidWco KSBzaG91bGQgb25seSBzZXQvY2xlYXIKPiAgICAgRVhDX0JSRUFLUE9JTlQgYml0IGluICJoZWRl bGVnIiBvZiAic3RydWN0IGt2bV92Y3B1X2NvbmZpZyIuCj4gMykgVGhlIGt2bV9yaXNjdl92Y3B1 X3N3YXBfaW5fZ3Vlc3Rfc3RhdGUoKSBtdXN0IHdyaXRlIHRoZQo+ICAgICAgSEVERUxFRyBjc3Ig YmVmb3JlIGVudGVyaW5nIHRoZSBHdWVzdC9WTS4KPiAKPiBSZWdhcmRzLAo+IEFudXAKPiAKClRo YW5rcyBmb3IgdGhlIHJldmlldyBhbmQgZGV0YWlsZWQgc3VnZ2VzdGlvbi4KTWF5YmUgd2UgY291 bGQgbWFrZSBpdCBhIGJpdCBlYXNpZXI6CjEpIFRoZSBrdm1fYXJjaF92Y3B1X2lvY3RsX3NldF9n dWVzdF9kZWJ1ZygpIG9ubHkgdXBkYXRlIHZjcHUtPmd1ZXN0X2RlYnVnCiAgIGFjY29yZGluZ2x5 LgoyKSBUaGUga3ZtX3Jpc2N2X3ZjcHVfc3dhcF9pbl9ndWVzdF9zdGF0ZSgpIGNoZWNrIHZjcHUt Pmd1ZXN0X2RlYnVnIGFuZAogICBzZXQvY2xlYXIgdGhlIEhFREVMRUcgY3NyIGFjY29yZGluZ2x5 LgoKQ291bGQgeW91IGNvbmZpcm0gaWYgdGhpcyBpcyBPSz8KSWYgeWVzLCBJIHdpbGwgcG9zdCBh bm90aGVyIHJldmlzaW9uLgoKUmVnYXJkcywKQ2hhbwoKPiA+ICsKPiA+ICsgICAgICAgcmV0dXJu IDA7Cj4gPiAgfQo+ID4KPiA+ICBzdGF0aWMgdm9pZCBrdm1fcmlzY3ZfdmNwdV9zZXR1cF9jb25m aWcoc3RydWN0IGt2bV92Y3B1ICp2Y3B1KQo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3Yva3Zt L3ZtLmMgYi9hcmNoL3Jpc2N2L2t2bS92bS5jCj4gPiBpbmRleCBjZTU4YmM0OGU1YjguLjczOTZi ODY1NGY0NSAxMDA2NDQKPiA+IC0tLSBhL2FyY2gvcmlzY3Yva3ZtL3ZtLmMKPiA+ICsrKyBiL2Fy Y2gvcmlzY3Yva3ZtL3ZtLmMKPiA+IEBAIC0xODYsNiArMTg2LDcgQEAgaW50IGt2bV92bV9pb2N0 bF9jaGVja19leHRlbnNpb24oc3RydWN0IGt2bSAqa3ZtLCBsb25nIGV4dCkKPiA+ICAgICAgICAg Y2FzZSBLVk1fQ0FQX1JFQURPTkxZX01FTToKPiA+ICAgICAgICAgY2FzZSBLVk1fQ0FQX01QX1NU QVRFOgo+ID4gICAgICAgICBjYXNlIEtWTV9DQVBfSU1NRURJQVRFX0VYSVQ6Cj4gPiArICAgICAg IGNhc2UgS1ZNX0NBUF9TRVRfR1VFU1RfREVCVUc6Cj4gPiAgICAgICAgICAgICAgICAgciA9IDE7 Cj4gPiAgICAgICAgICAgICAgICAgYnJlYWs7Cj4gPiAgICAgICAgIGNhc2UgS1ZNX0NBUF9OUl9W Q1BVUzoKPiA+IC0tCj4gPiAyLjE3LjEKPiA+Cj4gPgo+ID4gLS0KPiA+IGt2bS1yaXNjdiBtYWls aW5nIGxpc3QKPiA+IGt2bS1yaXNjdkBsaXN0cy5pbmZyYWRlYWQub3JnCj4gPiBodHRwOi8vbGlz dHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2t2bS1yaXNjdgo=