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Wed, 28 Jan 2026 08:26:15 -0800 (PST) Received: from [192.168.1.4] ([183.195.22.224]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c642487f1f5sm2818275a12.0.2026.01.28.08.26.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Jan 2026 08:26:15 -0800 (PST) Message-ID: <4a717b95-e7c7-4a9a-b98f-37df63602a2a@gmail.com> Date: Thu, 29 Jan 2026 00:25:17 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v1 0/2] tests/qtest: Add RISC-V IOMMU bare-metal test using iommu-testdev To: Daniel Henrique Barboza , Alistair Francis , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Tao Tang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, hust-os-kernel-patches@googlegroups.com References: <97143bc3-b473-4e72-877c-b3bf9a70819d@ventanamicro.com> From: Chao Liu In-Reply-To: <97143bc3-b473-4e72-877c-b3bf9a70819d@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pf1-x442.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Daniel, Thanks for the review and the kind words! On 1/28/2026 10:42 PM, Daniel Henrique Barboza wrote: > > > On 1/28/2026 9:09 AM, Chao Liu wrote: >> Hi, >> >> This patch series adds a bare-metal qtest for the RISC-V IOMMU using the >> iommu-testdev framework. The test exercises address translation paths >> without requiring a full guest OS boot. >> >> Motivation >> ---------- >> >> The existing RISC-V IOMMU qtest (riscv-iommu-test.c) focuses on PCI device >> enumeration and register-level validation: >> - PCI configuration space verification (vendor/device ID) >> - Register reset value checks >> - Queue initialization procedures (CQ/FQ/PQ) >> >> However, it does not test the actual address translation functionality. >> This new test fills that gap by using iommu-testdev to trigger DMA >> transactions and validate the IOMMU's translation logic. >> >> Comparison with Existing Test >> ----------------------------- >> >> | Feature               | riscv-iommu-test.c | iommu-riscv-test.c (new) | >> |-----------------------|--------------------|--------------------------| >> | PCI config            | Yes                | No                       | >> | Register reset        | Yes                | No                       | >> | Queue init            | Yes                | Yes (via helper)         | >> | Bare translation      | No                 | Yes                      | >> | S-stage (SV39)        | No                 | Yes                      | >> | G-stage (SV39x4)      | No                 | Yes                      | >> | Nested translation    | No                 | Yes                      | >> | DMA verification      | No                 | Yes                      | >> | Uses iommu-testdev    | No                 | Yes                      | >> >> The new test provides: >> - Device context (DC) configuration and validation >> - SV39 page table walks for S-stage translation >> - SV39x4 page table walks for G-stage translation >> - Nested translation combining both stages >> - FCTL register constraint validation >> - End-to-end DMA verification > > I have a customized environment just to test IOMMU stuff (boot an Ubuntu emulated RISC-V host, see if the riscv-iommu works with a PCI net card). And even then this kind of test is limited by the amount of stuff the current Linux driver is capable of doing. And yet I have to at least give it a try with every IOMMU change/fix sent ... This new test will give us additional coverage that neither the existing test nor my manual testing can provide. > > Thank you for the time and effort putting into this work. This is really remarkable. > I'm glad this patch series can help us better test the RISC-V IOMMU. The iommu-testdev framework makes it possible to exercise translation paths directly without booting a full guest OS, which should make regression testing much faster and more deterministic. >> >> Note: The current implementation only supports SV39/SV39x4. Support for >> SV48/SV48x4/SV57/SV57x4 can be added in future patches. >> >> Testing >> ------- >> >> QTEST_QEMU_BINARY=./build/qemu-system-riscv64 \ >>    ./build/tests/qtest/iommu-riscv-test --tap -k >> >> Question for Maintainers >> ------------------------ >> >> The existing riscv-iommu-test.c and the new iommu-riscv-test.c serve >> complementary purposes. Would it be beneficial to merge these two tests >> into a single source file for easier maintenance? This would consolidate >> all RISC-V IOMMU testing in one place while preserving both the >> register-level and translation-level test coverage. > > I'll give my non-maintainer opinion because I happen to be the author of riscv-iommu-test.c: as long as we preserve the existing tests for both files I'm ok with it. Maybe there are code re-use opportunities that will be exposed when merging the 2 together. > > But I believe this can wait. We should push this upstream first (or at least get it queued into the maintainer's tree). > > I share the same view. That's exactly why I didn't merge them directly in this series - the two tests serve different purposes (register-level vs translation-level), and keeping them separate for now makes the review process cleaner. We can explore merging opportunities later once this is upstream. Thanks, Chao > Thanks, > Daniel > >> >> Thanks, >> Chao >> >> Chao Liu (2): >>    tests/qtest/libqos: Add RISC-V IOMMU helper library >>    tests/qtest: Add RISC-V IOMMU bare-metal test >> >>   MAINTAINERS                          |   2 + >>   tests/qtest/iommu-riscv-test.c       | 279 +++++++++++++++++++ >>   tests/qtest/libqos/meson.build       |   2 +- >>   tests/qtest/libqos/qos-riscv-iommu.c | 400 +++++++++++++++++++++++++++ >>   tests/qtest/libqos/qos-riscv-iommu.h | 172 ++++++++++++ >>   tests/qtest/meson.build              |   5 +- >>   6 files changed, 858 insertions(+), 2 deletions(-) >>   create mode 100644 tests/qtest/iommu-riscv-test.c >>   create mode 100644 tests/qtest/libqos/qos-riscv-iommu.c >>   create mode 100644 tests/qtest/libqos/qos-riscv-iommu.h >> >> -- >> 2.52.0 >> >