From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01B11C27C50 for ; Mon, 3 Jun 2024 17:42:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jPZn82BX0NFlrgRYcQ7VGw8w0w2KCWNEfMLQ52Ny3+o=; b=d25rOuSLDRWHJc 75/u+OVgkDC7l00bwuK40sMdhfo+G3A0Be1772NkD6VKfOIJ3xU7pceoa5yUKEHOTPnKMcXo1jkU9 W44v8ZY52BcBy7kzbIWYhcZVTr7vjkAho28+vYLORghCYwqlw4lbkbSN5Pukl/VyoCh48n+tjD6TD 7JunDMrHZclpNJ1015t2JMNrz+Idin2mcE85mmh1rK6Wzq6MTA3eduEON4IwGtTRTDm2oUB5DuvBU lRNk2uR6ZdRgrNyA0iKhaQhqdzVMVHflGlVDyoYlei2pAQJmA+BLJNja34zPTluVmrvYoznnkiDqG bbAQa3wZmt3I3DXTLPoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEBh7-0000000HXKT-0kNY; Mon, 03 Jun 2024 17:42:05 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEBh4-0000000HXJR-0esG for linux-arm-kernel@lists.infradead.org; Mon, 03 Jun 2024 17:42:04 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 453HfsKw090374; Mon, 3 Jun 2024 12:41:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717436514; bh=TRuU8G9/d6lkp3hInz5RWXba11O8+BAQ5y7S3nHRwEw=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=PJrzINqcZ9Rdj/ryi7UrbPQqzzmZffuvavnkkk/PnSsSErwZfikiEhpuSmLlek7lq dBP8JRq4FoevchYIgWbcsnxJsyIE/qbSEztaHvDl6FwEWkls4hBlILYfoqtaiERt6Q H2rgG3+ORj5DUoQ1YfvMGQLKcSd9QFQ1hmwjYw3M= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 453HfsgA032152 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 3 Jun 2024 12:41:54 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 3 Jun 2024 12:41:54 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 3 Jun 2024 12:41:54 -0500 Received: from [172.24.227.94] (uda0132425.dhcp.ti.com [172.24.227.94]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 453HfoOg069313; Mon, 3 Jun 2024 12:41:51 -0500 Message-ID: <4ac40139-eda0-4f6a-8bbe-99110605f91e@ti.com> Date: Mon, 3 Jun 2024 23:11:49 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/4] Add overlays to disable optional hardware in k3-am6xx-phycore-som boards To: Nathan Morrisson , , , , , CC: , , , , References: <20240528225137.3629698-1-nmorrisson@phytec.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <20240528225137.3629698-1-nmorrisson@phytec.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240603_104202_317556_4508DD4C X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Nathan, On 29/05/24 04:21, Nathan Morrisson wrote: > Add three overlays to disable the eth phy, rtc, and spi nor. These > overlays will be used to disable device tree nodes for components > that are optionally not populated. > > v2: > - Add build time tests in makefile > > Nathan Morrisson (4): > arm64: dts: ti: k3-am64-phycore-som: Add serial_flash label > arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable eth phy > arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable rtc > arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disabl spi nor > > arch/arm64/boot/dts/ti/Makefile | 17 +++++++++++++++++ > .../boot/dts/ti/k3-am64-phycore-som.dtsi | 2 +- > .../ti/k3-am6xx-phycore-disable-eth-phy.dtso | 19 +++++++++++++++++++ > .../dts/ti/k3-am6xx-phycore-disable-rtc.dtso | 15 +++++++++++++++ > .../ti/k3-am6xx-phycore-disable-spi-nor.dtso | 15 +++++++++++++++ > 5 files changed, 67 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso > create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso > create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso > I am not sure if this a common practice to have overlays to disable missing components (at least I dont see such dtso in kernel). I would like to see an what DT maintainers feel as such dtsos can explode in numbers. Is this something that U-Boot can detect and fix up for the Linux DT? Unpopulated SPI flash and RTC should ideally not be an issue as drivers would gracefully fail albeit with some sort of error msg. Not so sure about Eth PHYs though. Also, Are these dtso's mutually exclusive? ie can SoM have SPI flash but not RTC, have RTC and SPI Flash but no ETH PHY? -- Regards Vignesh _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E85D0135A6F; Mon, 3 Jun 2024 17:42:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717436529; cv=none; b=X/EGjX+b327Mn/mXuqokKFf4+c+QXqKnBg5gBalxXbxlrUJaG/u5Q5ra4/HeCfX2QVnS8M/l7t2nkEmaR2lgybDS6+XjJoui1leFGnmL3bZ3tOoSyE/6t+chhgDD27wFzsj/0ZIufi0FQTl8Se2XJ0vrKMCRsu6/iy+jWoLWQUE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717436529; c=relaxed/simple; bh=FTMHYBDXrMSnzSW1m3RkobvbHdA+rKpO/+FvnIJ+Qt4=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=AWKO8JNzjQjmG6TvbQYOfJkB2LqKUDAp6S0OorJbYpcs6m1jdM+6jDRJPs8aKhUWsKTfT6ABWx5RblRFOq4Uo3HTNuFgiRIxvG8Um3xzrV7b+pJ8TgjwwkKIb+cDN+3pwbczL4uzj4GlL3FVxyK9NNT5yE1VzxJGzGbtH2kzWts= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=PJrzINqc; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PJrzINqc" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 453HfsKw090374; Mon, 3 Jun 2024 12:41:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717436514; bh=TRuU8G9/d6lkp3hInz5RWXba11O8+BAQ5y7S3nHRwEw=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=PJrzINqcZ9Rdj/ryi7UrbPQqzzmZffuvavnkkk/PnSsSErwZfikiEhpuSmLlek7lq dBP8JRq4FoevchYIgWbcsnxJsyIE/qbSEztaHvDl6FwEWkls4hBlILYfoqtaiERt6Q H2rgG3+ORj5DUoQ1YfvMGQLKcSd9QFQ1hmwjYw3M= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 453HfsgA032152 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 3 Jun 2024 12:41:54 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 3 Jun 2024 12:41:54 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 3 Jun 2024 12:41:54 -0500 Received: from [172.24.227.94] (uda0132425.dhcp.ti.com [172.24.227.94]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 453HfoOg069313; Mon, 3 Jun 2024 12:41:51 -0500 Message-ID: <4ac40139-eda0-4f6a-8bbe-99110605f91e@ti.com> Date: Mon, 3 Jun 2024 23:11:49 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/4] Add overlays to disable optional hardware in k3-am6xx-phycore-som boards To: Nathan Morrisson , , , , , CC: , , , , References: <20240528225137.3629698-1-nmorrisson@phytec.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <20240528225137.3629698-1-nmorrisson@phytec.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hi Nathan, On 29/05/24 04:21, Nathan Morrisson wrote: > Add three overlays to disable the eth phy, rtc, and spi nor. These > overlays will be used to disable device tree nodes for components > that are optionally not populated. > > v2: > - Add build time tests in makefile > > Nathan Morrisson (4): > arm64: dts: ti: k3-am64-phycore-som: Add serial_flash label > arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable eth phy > arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable rtc > arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disabl spi nor > > arch/arm64/boot/dts/ti/Makefile | 17 +++++++++++++++++ > .../boot/dts/ti/k3-am64-phycore-som.dtsi | 2 +- > .../ti/k3-am6xx-phycore-disable-eth-phy.dtso | 19 +++++++++++++++++++ > .../dts/ti/k3-am6xx-phycore-disable-rtc.dtso | 15 +++++++++++++++ > .../ti/k3-am6xx-phycore-disable-spi-nor.dtso | 15 +++++++++++++++ > 5 files changed, 67 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso > create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso > create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso > I am not sure if this a common practice to have overlays to disable missing components (at least I dont see such dtso in kernel). I would like to see an what DT maintainers feel as such dtsos can explode in numbers. Is this something that U-Boot can detect and fix up for the Linux DT? Unpopulated SPI flash and RTC should ideally not be an issue as drivers would gracefully fail albeit with some sort of error msg. Not so sure about Eth PHYs though. Also, Are these dtso's mutually exclusive? ie can SoM have SPI flash but not RTC, have RTC and SPI Flash but no ETH PHY? -- Regards Vignesh