Re: [PATCH i-g-t v3 1/1] tests/intel/xe_exec_system_allocator: Added 64k alignment support

["Sharma, Nishit" <nishit.sharma@intel.com>]

On 11/28/2025 10:08 AM, Sobin Thomas wrote:
> The original test for madvise split vm only supported 4 KB alignment,
> which failed certain hardware such as PVC that required 64 KB page
> alignment. The test has been updated to include support for 64 KB
> page alignment.

The original test for madvise split vm only supported 4KB alignment
which failed in hardware such as PVC which require 64KB page alignment.
Test has been updated with 64KB alignment in case of PVC and 4KB alignment as
default.

>
> ver2:
>   - Added check for PVC.
>
> ver3:
>   - Moved declarations in MADVISE_SPLIT_VMA scope. (Nishit)
>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>   tests/intel/xe_exec_system_allocator.c | 25 +++++++++++++++++++------
>   1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/tests/intel/xe_exec_system_allocator.c b/tests/intel/xe_exec_system_allocator.c
> index b88967e58..c54a52690 100644
> --- a/tests/intel/xe_exec_system_allocator.c
> +++ b/tests/intel/xe_exec_system_allocator.c
> @@ -1251,17 +1251,30 @@ xe_vm_parse_execute_madvise(int fd, uint32_t vm, struct test_exec_data *data,
>   	}
>   
>   	if (flags & MADVISE_SPLIT_VMA) {
> +		uint16_t dev_id = intel_get_drm_devid(fd);
> +		uint64_t split_addr, split_size;
> +		uint64_t alignment = SZ_4K;
> +
> +		if (IS_PONTEVECCHIO(dev_id))
> +			alignment = SZ_64K;
> +
>   		if (bo_size)
> -			bo_size = ALIGN(bo_size, SZ_4K);
> +			bo_size = ALIGN(bo_size, alignment);
> +
> +		split_addr = to_user_pointer(data) + bo_size/2;
> +		split_addr = ALIGN(split_addr, alignment);
> +		split_size = bo_size / 2;
> +		split_size = ALIGN(split_size, alignment);
>   
>   		bo_flags = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
>   		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id),
>   				  bo_flags);
> -		xe_vm_bind_async(fd, vm, 0, bo, 0, to_user_pointer(data) + bo_size / 2,
> -				 bo_size / 2, 0, 0);
>   
> -		__xe_vm_bind_assert(fd, vm, 0, 0, 0, to_user_pointer(data) + bo_size / 2,
> -				    bo_size / 2, DRM_XE_VM_BIND_OP_MAP,
> +		xe_vm_bind_async(fd, vm, 0, bo, 0, split_addr,
> +				 split_size, 0, 0);
> +
> +		__xe_vm_bind_assert(fd, vm, 0, 0, 0, split_addr,
> +				    split_size, DRM_XE_VM_BIND_OP_MAP,
>   				    DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR, sync,
>   				    1, 0, 0);
>   		xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, FIVE_SEC);
> @@ -1269,7 +1282,7 @@ xe_vm_parse_execute_madvise(int fd, uint32_t vm, struct test_exec_data *data,
>   		gem_close(fd, bo);
>   		bo = 0;
>   
> -		xe_vm_madvise_atomic_attr(fd, vm, to_user_pointer(data), bo_size / 2,
> +		xe_vm_madvise_atomic_attr(fd, vm, split_addr, split_size,
>   					  DRM_XE_ATOMIC_GLOBAL);
>   	}
>   

Modify description. Rest LGTM

Reviewed-by: Nishit Sharma <nishit.sharma@intel.com>