From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
dbarboza@ventanamicro.com
Subject: Re: [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc
Date: Sat, 26 Apr 2025 00:35:52 +0200 [thread overview]
Message-ID: <4cfc3a69-bae7-41ae-9f82-13eee8a8164e@linaro.org> (raw)
In-Reply-To: <20250425165055.807801-1-richard.henderson@linaro.org>
On 25/4/25 18:50, Richard Henderson wrote:
> This is an alternate, but less exact approach. It assumes that there
> will never be a 16 or 48-bit csr write instruction. This feels dirtier,
> but it's a fair assumption involves much less faff.
I prefer the other safer version which properly propagate $ra, which
could be useful for callees.
next prev parent reply other threads:[~2025-04-25 22:42 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-25 16:50 [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 16:50 ` [PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw Richard Henderson
2025-04-25 22:02 ` Daniel Henrique Barboza
2025-04-25 16:50 ` [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 22:20 ` Daniel Henrique Barboza
2025-04-26 14:12 ` Richard Henderson
2025-04-25 22:35 ` Philippe Mathieu-Daudé [this message]
2025-04-26 8:30 ` [PATCH alternate 0/2] " Daniel Henrique Barboza
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