Re: [PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions

["Nutty Liu" <liujingqi@lanxincomputing.com>]

On 6/27/2025 9:21 PM, Max Chou wrote:
> According to the RISC-V instruction set manual, the minimum VLEN needs
> to respect the following extensions:
>
>    Extension     Minimum VLEN
> * V             128
> * Zve64[d|f|x]   64
> * Zve32[f|x]     32
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/tcg/tcg-cpu.c | 13 +++++++++++--
>   1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 163e7ce3642..187534009dd 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -416,12 +416,21 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
>   static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
>                                    Error **errp)
>   {
> +    uint32_t min_vlen;
>       uint32_t vlen = cfg->vlenb << 3;
>   
> -    if (vlen > RV_VLEN_MAX || vlen < 128) {
> +    if (riscv_has_ext(env, RVV)) {
> +        min_vlen = 128;
> +    } else if (cfg->ext_zve64x) {
> +        min_vlen = 64;
> +    } else if (cfg->ext_zve32x) {
> +        min_vlen = 32;
> +    }
> +
> +    if (vlen > RV_VLEN_MAX || vlen < min_vlen) {
>           error_setg(errp,
>                      "Vector extension implementation only supports VLEN "
> -                   "in the range [128, %d]", RV_VLEN_MAX);
> +                   "in the range [%d, %d]", min_vlen, RV_VLEN_MAX);
>           return;
>       }
>   

Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>

Thanks,
Nutty