diff for duplicates of <4dfaffa99292bf8e36791ea9a68de75e@mail.gmail.com> diff --git a/a/1.txt b/N1/1.txt index 74a00e3..8f38c07 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,9 +1,9 @@ > -----Original Message----- -> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com] +> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com] > Sent: Monday, February 14, 2011 10:39 AM > To: Andrei Warkentin -> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com; -> linux-arm-kernel@lists.infradead.org; Catalin Marinas +> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com; +> linux-arm-kernel at lists.infradead.org; Catalin Marinas > Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way > operation can cause data corruption > @@ -215,3 +215,10 @@ aux_val, __u32 aux_mask) Cache size: %d B\n", -- 1.6.0.4 +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0003-ARM-l2x0-Errata-fix-for-flush-by-Way-operation-can.patch +Type: application/octet-stream +Size: 6061 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20110215/2e6980b7/attachment-0001.obj> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 1645fb1..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,6 +0,0 @@ -Content-Type: application/octet-stream; - name="0003-ARM-l2x0-Errata-fix-for-flush-by-Way-operation-can.patch" -Content-Disposition: attachment; - filename="0003-ARM-l2x0-Errata-fix-for-flush-by-Way-operation-can.patch" -Content-Transfer-Encoding: base64 -X-Attachment-Id: 25153e06c26ccd48_0.1 diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 2395e2b..0000000 --- a/a/2.txt +++ /dev/null @@ -1,179 +0,0 @@ -From 4063a3881e67197443cf447beada0e5265071828 Mon Sep 17 00:00:00 2001 -From: Santosh Shilimkar <santosh.shilimkar@ti.com> -Date: Fri, 14 Jan 2011 14:16:04 +0530 -Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption - -PL310 implements the Clean & Invalidate by Way L2 cache maintenance -operation (offset 0x7FC). This operation runs in background so that -PL310 can handle normal accesses while it is in progress. Under very -rare circumstances, due to this erratum, write data can be lost when -PL310 treats a cacheable write transaction during a Clean & Invalidate -by Way operation. - -Workaround: -Disable Write-Back and Cache Linefill (Debug Control Register) -Clean & Invalidate by Way (0x7FC) -Re-enable Write-Back and Cache Linefill (Debug Control Register) - -Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> -Cc: Catalin Marinas <catalin.marinas@arm.com> ---- - arch/arm/Kconfig | 13 ++++++++++++- - arch/arm/include/asm/outercache.h | 1 + - arch/arm/mach-omap2/Kconfig | 3 +++ - arch/arm/mach-omap2/omap4-common.c | 7 +++++++ - arch/arm/mm/cache-l2x0.c | 28 +++++++++++++++------------- - 5 files changed, 38 insertions(+), 14 deletions(-) - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 5cff165..ebadd95 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231 - - config PL310_ERRATA_588369 - bool "Clean & Invalidate maintenance operations do not invalidate clean lines" -- depends on CACHE_L2X0 && ARCH_OMAP4 -+ depends on CACHE_L2X0 && CACHE_PL310 - help - The PL310 L2 cache controller implements three types of Clean & - Invalidate maintenance operations: by Physical Address -@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622 - visible impact on the overall performance or power consumption of the - processor. - -+config PL310_ERRATA_727915 -+ bool "Background Clean & Invalidate by Way operation can cause data corruption" -+ depends on CACHE_L2X0 && CACHE_PL310 -+ help -+ PL310 implements the Clean & Invalidate by Way L2 cache maintenance -+ operation (offset 0x7FC). This operation runs in background so that -+ PL310 can handle normal accesses while it is in progress. Under very -+ rare circumstances, due to this erratum, write data can be lost when -+ PL310 treats a cacheable write transaction during a Clean & -+ Invalidate by Way operation Note that this errata uses Texas -+ Instrument's secure monitor api to implement the work around. - endmenu - - source "arch/arm/common/Kconfig" -diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h -index fc19009..348d513 100644 ---- a/arch/arm/include/asm/outercache.h -+++ b/arch/arm/include/asm/outercache.h -@@ -31,6 +31,7 @@ struct outer_cache_fns { - #ifdef CONFIG_OUTER_CACHE_SYNC - void (*sync)(void); - #endif -+ void (*set_debug)(unsigned long); - }; - - #ifdef CONFIG_OUTER_CACHE -diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig -index f285dd7..fd11ab4 100644 ---- a/arch/arm/mach-omap2/Kconfig -+++ b/arch/arm/mach-omap2/Kconfig -@@ -45,7 +45,10 @@ config ARCH_OMAP4 - select CPU_V7 - select ARM_GIC - select LOCAL_TIMERS -+ select CACHE_L2X0 -+ select CACHE_PL310 - select PL310_ERRATA_588369 -+ select PL310_ERRATA_727915 - select ARM_ERRATA_720789 - select ARCH_HAS_OPP - select PM_OPP if PM -diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c -index 1926864..9ef8c29 100644 ---- a/arch/arm/mach-omap2/omap4-common.c -+++ b/arch/arm/mach-omap2/omap4-common.c -@@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void) - omap_smc1(0x102, 0x0); - } - -+static void omap4_l2x0_set_debug(unsigned long val) -+{ -+ /* Program PL310 L2 Cache controller debug register */ -+ omap_smc1(0x100, val); -+} -+ - static int __init omap_l2_cache_init(void) - { - u32 aux_ctrl = 0; -@@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void) - * specific one - */ - outer_cache.disable = omap4_l2x0_disable; -+ outer_cache.set_debug = omap4_l2x0_set_debug; - - return 0; - } -diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c -index 170c9bb..a8caee4 100644 ---- a/arch/arm/mm/cache-l2x0.c -+++ b/arch/arm/mm/cache-l2x0.c -@@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long addr) - writel_relaxed(addr, base + L2X0_INV_LINE_PA); - } - --#ifdef CONFIG_PL310_ERRATA_588369 -+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) - static void debug_writel(unsigned long val) - { -- extern void omap_smc1(u32 fn, u32 arg); -- -- /* -- * Texas Instrument secure monitor api to modify the -- * PL310 Debug Control Register. -- */ -- omap_smc1(0x100, val); -+ if (outer_cache.set_debug) -+ outer_cache.set_debug(val); -+ else -+ writel(val, l2x0_base + L2X0_DEBUG_CTRL); -+} -+#else -+/* Optimised out for non-errata case */ -+static inline void debug_writel(unsigned long val) -+{ - } -+#endif - -+#ifdef CONFIG_PL310_ERRATA_588369 - static inline void l2x0_flush_line(unsigned long addr) - { - void __iomem *base = l2x0_base; -@@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long addr) - } - #else - --/* Optimised out for non-errata case */ --static inline void debug_writel(unsigned long val) --{ --} -- - static inline void l2x0_flush_line(unsigned long addr) - { - void __iomem *base = l2x0_base; -@@ -119,9 +118,11 @@ static void l2x0_flush_all(void) - - /* clean all ways */ - spin_lock_irqsave(&l2x0_lock, flags); -+ debug_writel(0x03); - writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); - cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); - cache_sync(); -+ debug_writel(0x00); - spin_unlock_irqrestore(&l2x0_lock, flags); - } - -@@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) - outer_cache.flush_all = l2x0_flush_all; - outer_cache.inv_all = l2x0_inv_all; - outer_cache.disable = l2x0_disable; -+ outer_cache.set_debug = NULL; - - printk(KERN_INFO "%s cache controller enabled\n", type); - printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", --- -1.6.0.4 diff --git a/a/content_digest b/N1/content_digest index e58f894..a9407ea 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,23 +4,18 @@ "ref\013596bec9184b117d6a1d02da8e017bf@mail.gmail.com\0" "ref\0AANLkTimjXG5-kEW=1vodnGo3Ct_xOS_HihdqN0TeL9ba@mail.gmail.com\0" "ref\033573d5cfc91cf45dc58ee861cccc2ae@mail.gmail.com\0" - "From\0Santosh Shilimkar <santosh.shilimkar@ti.com>\0" - "Subject\0RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption\0" + "From\0santosh.shilimkar@ti.com (Santosh Shilimkar)\0" + "Subject\0[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption\0" "Date\0Tue, 15 Feb 2011 12:44:17 +0530\0" - "To\0linux-arm-kernel@lists.infradead.org" - " Andrei Warkentin <andreiw@motorola.com>\0" - "Cc\0linux-omap@vger.kernel.org" - Kevin Hilman <khilman@ti.com> - tony@atomide.com - " Catalin Marinas <catalin.marinas@arm.com>\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "> -----Original Message-----\n" - "> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]\n" + "> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]\n" "> Sent: Monday, February 14, 2011 10:39 AM\n" "> To: Andrei Warkentin\n" - "> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;\n" - "> linux-arm-kernel@lists.infradead.org; Catalin Marinas\n" + "> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;\n" + "> linux-arm-kernel at lists.infradead.org; Catalin Marinas\n" "> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way\n" "> operation can cause data corruption\n" ">\n" @@ -231,188 +226,13 @@ " \tprintk(KERN_INFO \"l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x,\n" "Cache size: %d B\\n\",\n" "-- \n" - 1.6.0.4 - "\01:2\0" - "fn\00003-ARM-l2x0-Errata-fix-for-flush-by-Way-operation-can.patch\0" - "b\0" - "From 4063a3881e67197443cf447beada0e5265071828 Mon Sep 17 00:00:00 2001\n" - "From: Santosh Shilimkar <santosh.shilimkar@ti.com>\n" - "Date: Fri, 14 Jan 2011 14:16:04 +0530\n" - "Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption\n" - "\n" - "PL310 implements the Clean & Invalidate by Way L2 cache maintenance\n" - "operation (offset 0x7FC). This operation runs in background so that\n" - "PL310 can handle normal accesses while it is in progress. Under very\n" - "rare circumstances, due to this erratum, write data can be lost when\n" - "PL310 treats a cacheable write transaction during a Clean & Invalidate\n" - "by Way operation.\n" - "\n" - "Workaround:\n" - "Disable Write-Back and Cache Linefill (Debug Control Register)\n" - "Clean & Invalidate by Way (0x7FC)\n" - "Re-enable Write-Back and Cache Linefill (Debug Control Register)\n" - "\n" - "Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>\n" - "Cc: Catalin Marinas <catalin.marinas@arm.com>\n" - "---\n" - " arch/arm/Kconfig | 13 ++++++++++++-\n" - " arch/arm/include/asm/outercache.h | 1 +\n" - " arch/arm/mach-omap2/Kconfig | 3 +++\n" - " arch/arm/mach-omap2/omap4-common.c | 7 +++++++\n" - " arch/arm/mm/cache-l2x0.c | 28 +++++++++++++++-------------\n" - " 5 files changed, 38 insertions(+), 14 deletions(-)\n" - "\n" - "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n" - "index 5cff165..ebadd95 100644\n" - "--- a/arch/arm/Kconfig\n" - "+++ b/arch/arm/Kconfig\n" - "@@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231\n" - " \n" - " config PL310_ERRATA_588369\n" - " \tbool \"Clean & Invalidate maintenance operations do not invalidate clean lines\"\n" - "-\tdepends on CACHE_L2X0 && ARCH_OMAP4\n" - "+\tdepends on CACHE_L2X0 && CACHE_PL310\n" - " \thelp\n" - " \t The PL310 L2 cache controller implements three types of Clean &\n" - " \t Invalidate maintenance operations: by Physical Address\n" - "@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622\n" - " \t visible impact on the overall performance or power consumption of the\n" - " \t processor.\n" - " \n" - "+config PL310_ERRATA_727915\n" - "+\tbool \"Background Clean & Invalidate by Way operation can cause data corruption\"\n" - "+\tdepends on CACHE_L2X0 && CACHE_PL310\n" - "+\thelp\n" - "+\t PL310 implements the Clean & Invalidate by Way L2 cache maintenance\n" - "+\t operation (offset 0x7FC). This operation runs in background so that\n" - "+\t PL310 can handle normal accesses while it is in progress. Under very\n" - "+\t rare circumstances, due to this erratum, write data can be lost when\n" - "+\t PL310 treats a cacheable write transaction during a Clean &\n" - "+\t Invalidate by Way operation Note that this errata uses Texas\n" - "+\t Instrument's secure monitor api to implement the work around.\n" - " endmenu\n" - " \n" - " source \"arch/arm/common/Kconfig\"\n" - "diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h\n" - "index fc19009..348d513 100644\n" - "--- a/arch/arm/include/asm/outercache.h\n" - "+++ b/arch/arm/include/asm/outercache.h\n" - "@@ -31,6 +31,7 @@ struct outer_cache_fns {\n" - " #ifdef CONFIG_OUTER_CACHE_SYNC\n" - " \tvoid (*sync)(void);\n" - " #endif\n" - "+\tvoid (*set_debug)(unsigned long);\n" - " };\n" - " \n" - " #ifdef CONFIG_OUTER_CACHE\n" - "diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig\n" - "index f285dd7..fd11ab4 100644\n" - "--- a/arch/arm/mach-omap2/Kconfig\n" - "+++ b/arch/arm/mach-omap2/Kconfig\n" - "@@ -45,7 +45,10 @@ config ARCH_OMAP4\n" - " \tselect CPU_V7\n" - " \tselect ARM_GIC\n" - " \tselect LOCAL_TIMERS\n" - "+\tselect CACHE_L2X0\n" - "+\tselect CACHE_PL310\n" - " \tselect PL310_ERRATA_588369\n" - "+\tselect PL310_ERRATA_727915\n" - " \tselect ARM_ERRATA_720789\n" - " \tselect ARCH_HAS_OPP\n" - " \tselect PM_OPP if PM\n" - "diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c\n" - "index 1926864..9ef8c29 100644\n" - "--- a/arch/arm/mach-omap2/omap4-common.c\n" - "+++ b/arch/arm/mach-omap2/omap4-common.c\n" - "@@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)\n" - " \tomap_smc1(0x102, 0x0);\n" - " }\n" - " \n" - "+static void omap4_l2x0_set_debug(unsigned long val)\n" - "+{\n" - "+\t/* Program PL310 L2 Cache controller debug register */\n" - "+\tomap_smc1(0x100, val);\n" - "+}\n" - "+\n" - " static int __init omap_l2_cache_init(void)\n" - " {\n" - " \tu32 aux_ctrl = 0;\n" - "@@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)\n" - " \t * specific one\n" - " \t*/\n" - " \touter_cache.disable = omap4_l2x0_disable;\n" - "+\touter_cache.set_debug = omap4_l2x0_set_debug;\n" - " \n" - " \treturn 0;\n" - " }\n" - "diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c\n" - "index 170c9bb..a8caee4 100644\n" - "--- a/arch/arm/mm/cache-l2x0.c\n" - "+++ b/arch/arm/mm/cache-l2x0.c\n" - "@@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long addr)\n" - " \twritel_relaxed(addr, base + L2X0_INV_LINE_PA);\n" - " }\n" - " \n" - "-#ifdef CONFIG_PL310_ERRATA_588369\n" - "+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)\n" - " static void debug_writel(unsigned long val)\n" - " {\n" - "-\textern void omap_smc1(u32 fn, u32 arg);\n" - "-\n" - "-\t/*\n" - "-\t * Texas Instrument secure monitor api to modify the\n" - "-\t * PL310 Debug Control Register.\n" - "-\t */\n" - "-\tomap_smc1(0x100, val);\n" - "+\tif (outer_cache.set_debug)\n" - "+\t\touter_cache.set_debug(val);\n" - "+\telse\n" - "+\t\twritel(val, l2x0_base + L2X0_DEBUG_CTRL);\n" - "+}\n" - "+#else\n" - "+/* Optimised out for non-errata case */\n" - "+static inline void debug_writel(unsigned long val)\n" - "+{\n" - " }\n" - "+#endif\n" - " \n" - "+#ifdef CONFIG_PL310_ERRATA_588369\n" - " static inline void l2x0_flush_line(unsigned long addr)\n" - " {\n" - " \tvoid __iomem *base = l2x0_base;\n" - "@@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long addr)\n" - " }\n" - " #else\n" - " \n" - "-/* Optimised out for non-errata case */\n" - "-static inline void debug_writel(unsigned long val)\n" - "-{\n" - "-}\n" - "-\n" - " static inline void l2x0_flush_line(unsigned long addr)\n" - " {\n" - " \tvoid __iomem *base = l2x0_base;\n" - "@@ -119,9 +118,11 @@ static void l2x0_flush_all(void)\n" - " \n" - " \t/* clean all ways */\n" - " \tspin_lock_irqsave(&l2x0_lock, flags);\n" - "+\tdebug_writel(0x03);\n" - " \twritel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);\n" - " \tcache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);\n" - " \tcache_sync();\n" - "+\tdebug_writel(0x00);\n" - " \tspin_unlock_irqrestore(&l2x0_lock, flags);\n" - " }\n" - " \n" - "@@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)\n" - " \touter_cache.flush_all = l2x0_flush_all;\n" - " \touter_cache.inv_all = l2x0_inv_all;\n" - " \touter_cache.disable = l2x0_disable;\n" - "+\touter_cache.set_debug = NULL;\n" - " \n" - " \tprintk(KERN_INFO \"%s cache controller enabled\\n\", type);\n" - " \tprintk(KERN_INFO \"l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\\n\",\n" - "-- \n" - 1.6.0.4 + "1.6.0.4\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: 0003-ARM-l2x0-Errata-fix-for-flush-by-Way-operation-can.patch\n" + "Type: application/octet-stream\n" + "Size: 6061 bytes\n" + "Desc: not available\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20110215/2e6980b7/attachment-0001.obj> -2187a4527711e71db82d8a283bc31bbaeec0e0d7ab4a7401f86cdeae91d246b3 +0a1bd220abb84662945aaa95dfe7285a1f1a5d9b4fb19623751d8cacaf38f60f
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.