From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:45169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QmblU-00035y-Kj for qemu-devel@nongnu.org; Thu, 28 Jul 2011 21:21:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QmblT-0008Kt-FO for qemu-devel@nongnu.org; Thu, 28 Jul 2011 21:21:24 -0400 Received: from mail-pz0-f43.google.com ([209.85.210.43]:62949) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QmblT-0008Kp-5G for qemu-devel@nongnu.org; Thu, 28 Jul 2011 21:21:23 -0400 Received: by pzk1 with SMTP id 1so5729817pzk.30 for ; Thu, 28 Jul 2011 18:21:22 -0700 (PDT) Message-ID: <4e320b10.0222440a.61f2.6c8c@mx.google.com> Date: Fri, 29 Jul 2011 10:21:17 +0900 From: tsnsaito@gmail.com In-Reply-To: References: <316f198de781f7b819456f433d84ead284769a71.1311606610.git.atar4qemu@gmail.com> <4e313a7e.c926440a.2e83.4a11@mx.google.com> <4e315024.11948e0a.4077.2795@mx.google.com> <4e3166e3.c323440a.2041.54f3@mx.google.com> MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] fix disabling interrupts in sun4u List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: blauwirbel@gmail.com, qemu-devel@nongnu.org At Thu, 28 Jul 2011 16:44:23 +0200, Artyom Tarasenko wrote: > On Thu, Jul 28, 2011 at 3:40 PM, wrote: > > At Thu, 28 Jul 2011 14:50:57 +0200, > > Artyom Tarasenko wrote: > >> On Thu, Jul 28, 2011 at 2:03 PM,   wrote: > >> > At Thu, 28 Jul 2011 13:51:08 +0200, > >> > Artyom Tarasenko wrote: > >> >> On Thu, Jul 28, 2011 at 12:31 PM,   wrote: > >> Do you have objections to this patch in its current form? > > > > No, I don't have any objections. > > > >> > The interrupts from APB would be reported by cpu_set_irq(), > >> > but cpu_set_irq() seems to generate interrupt_vector_n traps. > >> > >> For me it's not obvious. The interrupt vector not just one line, but > >> the vector, which is written in the corresponding CPU register (also > >> missing in the current qemu implementation). On the real hardware the > >> vector is created by the IOMMU (PBM/APB/...). If qemu intends to > >> support multiple chipsets, we should keep it the way it's done on the > >> real hardware (for instance the interrupt vectors for on-board devices > >> on Ultra-1 and E6500 are not the same). > > > > Sorry, I can't keep up with this vector thing... > > Does the CPU receive hardware interrupts as interrupt_vector traps > > (trap type=3D0x60) regardless of the kind of the interrupt controller, > > doesn't it? >=20 > It does indeed, but it also stores the interrupt vector identifying > the initiator device, in a CPU register readable with asi 0x7f . > What would APB pass to the cpu_set_irq? I see the three following variant= s: >=20 > a) it passes the PCI interrupt id, which is translated to the > interrupt vector in cpu_set_irq() > b) it passes the vector. This implies that 2048 (0-0x7ff) CPU > interrupts have to be allocated. > c) hack combining a+b: allocate only the interrupts known to be used > and translate an internal interrupt id to a vector. >=20 > The variant "a" is bad because it doesn't allow support for different > chipsets. The variant "b" is bad because qemu has to allocate way too > many interrupts. Only few of them will be used actually. The variant > "c" is bad, well, because it's a hack. >=20 > That's why I suggest using another interface between APB and CPU. Thanks, I understand the reason for introducing a diffent interface for device interrupts. It might be difficult to implement the interface as the set_irq callback. > >> I'd suggest APB shall use some other interface for communicating > >> interrupts to the CPU. Something like > >> cpu_receive_ivec(interrupt_vector). > >> > >> >> >> Signed-off-by: Artyom Tarasenko > >> >> >> --- > >> >> >>  hw/sun4u.c |    6 ++++-- > >> >> >>  1 files changed, 4 insertions(+), 2 deletions(-) > >> >> >> > >> >> >> diff --git a/hw/sun4u.c b/hw/sun4u.c > >> >> >> index d7dcaf0..7f95aeb 100644 > >> >> >> --- a/hw/sun4u.c > >> >> >> +++ b/hw/sun4u.c > >> >> >> @@ -255,7 +255,7 @@ void cpu_check_irqs(CPUState *env) > >> >> >>          pil |=3D 1 << 14; > >> >> >>      } > >> >> >> > >> >> >> -    if (!pil) { > >> >> >> +    if (pil < (2 << env->psrpil)){ > >> >> >>          if (env->interrupt_request & CPU_INTERRUPT_HARD) { > >> >> >>              CPUIRQ_DPRINTF("Reset CPU IRQ (current inter= rupt %x)\n", > >> >> >>                             env->interrupt_index); > >> >> >> @@ -287,10 +287,12 @@ void cpu_check_irqs(CPUState *env) > >> >> >>                  break; > >> >> >>              } > >> >> >>          } > >> >> >> -    } else { > >> >> >> +    } else if (env->interrupt_request & CPU_INTERRUPT_HARD) { > >> >> >>          CPUIRQ_DPRINTF("Interrupts disabled, pil=3D%08x pi= l_in=3D%08x softint=3D%08x " > >> >> >>                         "current interrupt %x\n", > >> >> >>                         pil, env->pil_in, env->softi= nt, env->interrupt_index); > >> >> >> +        env->interrupt_index =3D 0; > >> >> >> +        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); > >> >> >>      } > >> >> >>  } > >> >> >> > >> >> >> -- > >> >> >> 1.7.3.4 > >> >> > > >> >> > > >> >> > ---- > >> >> > Tsuneo Saito > >> >> > > >> >> > >> >> > >> >> > >> >> -- > >> >> Regards, > >> >> Artyom Tarasenko > >> >> > >> >> solaris/sparc under qemu blog: http://tyom.blogspot.com/ > >> > > >> > ---- > >> > Tsuneo Saito > >> > > >> > >> -- > >> Regards, > >> Artyom Tarasenko > >> > >> solaris/sparc under qemu blog: http://tyom.blogspot.com/ > > > > ---- > > Tsuneo Saito > > >=20 >=20 >=20 > --=20 > Regards, > Artyom Tarasenko >=20 > solaris/sparc under qemu blog: http://tyom.blogspot.com/ ---- Tsuneo Saito