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Mon, 30 Oct 2023 10:28:10 -0700 (PDT) Message-ID: <4eef627e-49ee-4d54-97c6-ea89eb772047@ventanamicro.com> Date: Mon, 30 Oct 2023 14:28:07 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Content-Language: en-US To: Max Chou , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Andrew Jones References: <20231026151828.754279-1-max.chou@sifive.com> <20231026151828.754279-7-max.chou@sifive.com> From: Daniel Henrique Barboza In-Reply-To: <20231026151828.754279-7-max.chou@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::112d; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 10/26/23 12:18, Max Chou wrote: > Vector crypto spec defines the NIST algorithm suite related extensions > (Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions. > > Signed-off-by: Max Chou > --- > target/riscv/cpu_cfg.h | 3 +++ > target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ > 2 files changed, 23 insertions(+) > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 935335e5721..fd07aa96a27 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -96,6 +96,9 @@ struct RISCVCPUConfig { > bool ext_zvksed; > bool ext_zvksh; > bool ext_zvkt; > + bool ext_zvkn; > + bool ext_zvknc; > + bool ext_zvkng; > bool ext_zmmul; > bool ext_zvfbfmin; > bool ext_zvfbfwma; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 1b08f27eee4..e460701a13c 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -499,6 +499,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + /* > + * Shorthand vector crypto extensions > + */ > + if (cpu->cfg.ext_zvknc) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > + } > + > + if (cpu->cfg.ext_zvkng) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); > + } > + > + if (cpu->cfg.ext_zvkn) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); > + } > + As a follow-up, we should move these vector validations to its own helper. We already have riscv_cpu_validate_v(), making it a good place to center all RVV related validations. For now: Reviewed-by: Daniel Henrique Barboza > if (cpu->cfg.ext_zvkt) { > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);