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Wed, 3 Jun 2026 14:10:16 GMT Received: from smtprelay05.wdc07v.mail.ibm.com ([172.16.1.72]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4egcwyg6hd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 Jun 2026 14:10:16 +0000 (GMT) Received: from smtpav03.dal12v.mail.ibm.com (smtpav03.dal12v.mail.ibm.com [10.241.53.102]) by smtprelay05.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 653EAFS633555118 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 3 Jun 2026 14:10:15 GMT Received: from smtpav03.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0791858056; Wed, 3 Jun 2026 14:10:15 +0000 (GMT) Received: from smtpav03.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 24A305803F; Wed, 3 Jun 2026 14:10:14 +0000 (GMT) Received: from mambor8.rchland.ibm.com (unknown [9.10.239.198]) by smtpav03.dal12v.mail.ibm.com (Postfix) with ESMTP; Wed, 3 Jun 2026 14:10:14 +0000 (GMT) Message-ID: <4ef1791085a32802185b2c68686aab273f4dfcbd.camel@linux.ibm.com> Subject: Re: [RFC PATCH 00/28] target/ppc: Moving instructions to decodetree specification From: Miles Glenn To: Chinmay Rath , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com Date: Wed, 03 Jun 2026 09:10:13 -0500 In-Reply-To: <285fdd30-f22d-4d4b-b8ee-5f04fccfca6d@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> <285fdd30-f22d-4d4b-b8ee-5f04fccfca6d@linux.ibm.com> Organization: IBM Content-Type: text/plain; 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envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 2026-06-03 at 17:09 +0530, Chinmay Rath wrote: > On 5/20/26 21:37, Chinmay Rath wrote: > > We recently had a QEMU decodetree hackathon at our org focusing on moving > > instructions to decodetree specification. I have consolidated the patches > > generated out of this effort in this series. Though I have done a round > > of review on all of them, might share some more review comments later. > > > > The checkpatch.pl script emits false error for a couple of patches which > > are of the following nature : > > > > TRANS(STWAT, do_st_atomic, DEF_MEMOP(MO_UL)) > > > > static bool trans_LDAT(DisasContext *ctx, arg_LDAT *a) > > ^ > > I see this happening in the last pointer argument in function > > definitions after macros (like TRANS(..) in this case). > > > > Richard, Peter, Stefan, > > Could you please advise if it would be okay to have the above false > > positive in the patches ? > Hi Chao, > I was wondering if you would be able to advise a way forward for this > checkpatch issue ? TIA. > > Gitlab CI: https://gitlab.com/rathc/qemu/-/pipelines/2540725424 > > Please note that check-python-tox and migration-compat-aarch64 from CI > > fails in the upstream master branch as seen in the following: > > https://gitlab.com/rathc/qemu/-/pipelines/2537246569 > > > > Thanks, > > Chinmay > Hi Glenn, > If possible, would you like to have a look at this series when you get a > chance ? TIA. Hi Chinmay, First, I'd like to thank you and everyone that worked on this for their efforts! This seems like one of those tasks that everyone knows is needed but everyone would rather work on other more interesting things (myself included). I would like to take a look at this series when I get the chance. I do have a lot on my plate right now, but hopefully I can get to it in the next week or so. Thanks, Glenn > > Thanks, > Chinmay > > Aboorva Devarajan (3): > > target/ppc: Move vector merge instructions to decodetree > > target/ppc: Move vector pack instructions to decodetree > > target/ppc: Move GPR atomic load/store instructions to decodetree > > > > Amit Machhiwal (2): > > target/ppc: Move fixed-point Shift insns to decodetree > > target/ppc: Move fixed-point byte-reversal store insns to decodetree > > > > Mukesh Kumar Chaurasiya (IBM) (2): > > target/ppc: convert slw,srw instruction via decode spec > > target/ppc: convert sraw[i] instruction via decode spec > > > > Nikhil Kumar Singh (3): > > target/ppc: Migrate extswsli to decodetree > > target/ppc: Migrate atomic loads to decodetree > > target/ppc: Convert cache instructions to decodetree > > > > Ojaswin Mujoo (7): > > target/ppc: Move isync instruction to decodetree. > > target/ppc: Convert b{a, l, la} to decode tree > > target/ppc: move various conditional branch insns to decodetree > > target/ppc: Fix TRANS* macro variadic arguments handling > > target/ppc: Move wait instruction to decodetree > > target/ppc: Move sleep & friends to decodetree > > target/ppc: Refactor sleep and its variants to use a common helper > > > > Shivang Upadhyay (4): > > target/ppc: Move Condition Register access instructions to decodetree. > > target/ppc: Move Condition Register logical instructions to > > decodetree. > > target/ppc: Move Fixed-Point Load/Store String instructions to > > decodetree. > > target/ppc: Move VMX integer arithmetic and BCD instructions to > > decodetree. > > > > Shivani Nittor (1): > > target/ppc : Convert mcrf to decode tree > > > > Tanushree Shah (2): > > target/ppc: Move rlwimi, rlwinm instructions to decodetree > > target/ppc: Move lmw, stmw instructions to decodetree > > > > Utkarsh Verma (1): > > target/ppc: Move st{b, h, w, d, q}cx instructions to decodetree > > > > Vishal Chourasia (3): > > target/ppc: Move mfmsr, mtmsr[d] instructions to decodetree > > target/ppc: Move byte-reverse instructions to decodetree > > target/ppc: Move system call and rfi instructions to decodetree > > > > target/ppc/helper.h | 100 +- > > target/ppc/insn32.decode | 244 ++ > > target/ppc/int_helper.c | 76 +- > > target/ppc/internal.h | 7 - > > target/ppc/mem_helper.c | 18 +- > > target/ppc/tcg-excp_helper.c | 10 +- > > target/ppc/translate.c | 2592 ++++------------- > > target/ppc/translate/branch-impl.c.inc | 181 ++ > > target/ppc/translate/fixedpoint-impl.c.inc | 936 ++++++ > > target/ppc/translate/misc-impl.c.inc | 175 ++ > > .../ppc/translate/processor-ctrl-impl.c.inc | 30 + > > target/ppc/translate/storage-ctrl-impl.c.inc | 117 + > > target/ppc/translate/vmx-impl.c.inc | 360 +-- > > target/ppc/translate/vmx-ops.c.inc | 41 - > > 14 files changed, 2529 insertions(+), 2358 deletions(-) > >