Re: [PATCH v4 2/5] drm/xe/xe_late_bind_fw: Convert late bind flag to mask

[Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>]

On 7/23/2026 1:37 AM, Badal Nilawar wrote:
> Replace the has_late_bind flag with a late_bind_mask to support
> multiple late bind firmware types.
>
> No functional change intended.
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/xe/xe_device.c       | 2 +-
>   drivers/gpu/drm/xe/xe_device_types.h | 4 ++--
>   drivers/gpu/drm/xe/xe_late_bind_fw.c | 5 ++++-
>   drivers/gpu/drm/xe/xe_pci.c          | 4 ++--
>   drivers/gpu/drm/xe/xe_pci_types.h    | 2 +-
>   5 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 4eed9a251e65..1849e1f072b4 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -738,7 +738,7 @@ static void vf_update_device_info(struct xe_device *xe)
>   	xe->info.has_heci_cscfi = 0;
>   	xe->info.has_heci_gscfi = 0;
>   	xe->info.has_i2c = 0;
> -	xe->info.has_late_bind = 0;
> +	xe->info.late_bind_mask = 0;
>   	xe->info.skip_guc_pc = 1;
>   	xe->info.skip_pcode = 1;
>   	xe->info.has_drm_ras = false;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 860ad322237f..db56d35f453d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -139,6 +139,8 @@ struct xe_device {
>   		u8 vm_max_level;
>   		/** @info.va_bits: Maximum bits of a virtual address */
>   		u8 va_bits;
> +		/** @info.late_bind_mask: Indicates supported late binding firmwares */
> +		u8 late_bind_mask;
>   
>   		/*
>   		 * Keep all flags below alphabetically sorted
> @@ -168,8 +170,6 @@ struct xe_device {
>   		u8 has_heci_gscfi:1;
>   		/** @info.has_i2c: Device has I2C controller */
>   		u8 has_i2c:1;
> -		/** @info.has_late_bind: Device has firmware late binding support */
> -		u8 has_late_bind:1;
>   		/** @info.has_llc: Device has a shared CPU+GPU last level cache */
>   		u8 has_llc:1;
>   		/** @info.has_mbx_power_limits: Device has support to manage power limits using
> diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_late_bind_fw.c
> index 1529a1de4051..8f3be55060f1 100644
> --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c
> +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c
> @@ -366,6 +366,7 @@ static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_id)
>   
>   static int xe_late_bind_fw_init(struct xe_late_bind *late_bind)
>   {
> +	struct xe_device *xe = late_bind_to_xe(late_bind);
>   	int ret;
>   	int fw_id;
>   
> @@ -374,6 +375,8 @@ static int xe_late_bind_fw_init(struct xe_late_bind *late_bind)
>   		return -ENOMEM;
>   
>   	for (fw_id = 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) {
> +		if (!(xe->info.late_bind_mask & BIT(fw_id)))
> +			continue;
>   		ret = __xe_late_bind_fw_init(late_bind, fw_id);
>   		if (ret)
>   			return ret;
> @@ -437,7 +440,7 @@ int xe_late_bind_init(struct xe_late_bind *late_bind)
>   	struct xe_device *xe = late_bind_to_xe(late_bind);
>   	int err;
>   
> -	if (!xe->info.has_late_bind)
> +	if (!xe->info.late_bind_mask)
>   		return 0;
>   
>   	if (!IS_ENABLED(CONFIG_INTEL_MEI_LB) || !IS_ENABLED(CONFIG_INTEL_MEI_GSC)) {
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 36d62927b969..283919fbbc04 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -421,10 +421,10 @@ static const struct xe_device_desc bmg_desc = {
>   	.has_gsc_nvm = 1,
>   	.has_heci_cscfi = 1,
>   	.has_i2c = true,
> -	.has_late_bind = true,
>   	.has_pre_prod_wa = 1,
>   	.has_soc_remapper_telem = true,
>   	.has_sriov = true,
> +	.late_bind_mask = BIT(XE_LB_FW_FAN_CONTROL),
>   	.max_gt_per_tile = 2,
>   	MULTI_LRC_MASK,
>   	.needs_scratch = true,
> @@ -802,7 +802,6 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>   	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
>   	xe->info.has_i2c = desc->has_i2c;
> -	xe->info.has_late_bind = desc->has_late_bind;
>   	xe->info.has_llc = desc->has_llc;
>   	xe->info.has_mert = desc->has_mert;
>   	xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
> @@ -818,6 +817,7 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.needs_scratch = desc->needs_scratch;
>   	xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
>   	xe->info.multi_lrc_mask = desc->multi_lrc_mask;
> +	xe->info.late_bind_mask = desc->late_bind_mask;
>   
>   	xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
>   				 xe_modparam.probe_display &&
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index fed509ff601e..d1d41c65133f 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -28,6 +28,7 @@ struct xe_device_desc {
>   	enum xe_platform platform;
>   
>   	u8 dma_mask_size;
> +	u8 late_bind_mask;
>   	u8 max_remote_tiles:2;
>   	u8 max_gt_per_tile:2;
>   	u8 multi_lrc_mask;
> @@ -47,7 +48,6 @@ struct xe_device_desc {
>   	u8 has_heci_gscfi:1;
>   	u8 has_heci_cscfi:1;
>   	u8 has_i2c:1;
> -	u8 has_late_bind:1;
>   	u8 has_llc:1;
>   	u8 has_mbx_power_limits:1;
>   	u8 has_mbx_thermal_info:1;