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Wed, 26 Aug 2026 04:54:56 -0700 (PDT) X-Received: by 2002:a05:6a00:6ca7:b0:848:2e7e:353a with SMTP id d2e1a72fcca58-8536ec13a78mr13481100b3a.0.1787745295712; Wed, 26 Aug 2026 04:54:55 -0700 (PDT) Received: from [10.217.219.186] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8535cf3e982sm793514b3a.54.2026.08.26.04.54.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Aug 2026 04:54:55 -0700 (PDT) Message-ID: <4efcdf15-286c-4bd6-a75f-77fbca07e7a4@oss.qualcomm.com> Date: Wed, 26 Aug 2026 17:24:48 +0530 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] i2c: qcom-geni: Use geni_se_set_rate() for setting source clock frequency To: Praveen Talari , konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-0-61171ab1cdce@oss.qualcomm.com> <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-7-61171ab1cdce@oss.qualcomm.com> <8af7a34a-da4f-492f-a51c-cc420edc5e6e@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=MqZiLWae c=1 sm=1 tr=0 ts=6a8ed410 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=4Fh5LKrImxLeDWyZwEgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: 1V7TRJv8181h5cbpOWNTpX0oCZEN0pou X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDA5OSBTYWx0ZWRfX0723IbCSQ4Ly 8a9RN3vo+/o7i9dim8PsZDvj0Qlf6qQxJrh4CECOjgOzm02kMVElwT01W4bA4BPtuPFootXwF6U QxplqDK+8FnodfiIEwzUQ0tem6t5IBYYFR97/XSgmO29ezDYiYODAhBLtEXvwzjOorBqWY7GJ9d jJI55w2lkzpGn6G4ML0tWMSI3OVSJaH+b6CNTuohAGdNd9sV3sKrBOasCZscdCGzIHdMDdqfU+5 61XBbC4Z3oo7p/f7dmDxxJZ/mElbWWfUSHj99H9A9tNpMu00FL9hJlhcPK9ORHRoJ/DhI4WdV8w Ldioa2SAFd0i3SvplBtigWfIx7I6CLoGh4JHS+I93kK26K1zDKsax2QCF10+G5gIlpkKIF0m1YG y1/OPyjVncwhU/IXgTiiBzjtLHCDfg2caUc566nf1NGiXWFETrYGDPpHmfm+9BPipqTELjemy7H 8Y3QsL9MNHUPV4dmGbw== X-Proofpoint-GUID: 1V7TRJv8181h5cbpOWNTpX0oCZEN0pou X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDA5OSBTYWx0ZWRfX7QRF5om3ZlF1 JVMygv+LMAg+BHhVGtD49EhUPEpgWx1ZRCfPqMKwH4rA9jI7Y0CmYuR5rhu/LJEeT6WWJ3nT0Gu UXklozrZfv8Km48wRENBgIaQUXJoOJU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-26_03,2026-08-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260099 On 8/25/2026 12:38 PM, Praveen Talari wrote: [...] >>> index a23554d101fd..4561e2d235d5 100644 >>> --- a/drivers/i2c/busses/i2c-qcom-geni.c >>> +++ b/drivers/i2c/busses/i2c-qcom-geni.c >>> @@ -213,11 +213,11 @@ static int geni_i2c_clk_map_idx(struct >>> geni_i2c_dev *gi2c) >>>       return -EINVAL; >>>   } >>>   -static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) >>> +static int qcom_geni_i2c_conf(struct geni_se *se) >>>   { >>>       struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); >>>       const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; >>> -    u32 val; >>> +    u32 val, ret; >>>         writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); >>>   @@ -233,6 +233,10 @@ static int qcom_geni_i2c_conf(struct geni_se >>> *se, unsigned long freq) >>>                    itr->clk_div, itr->t_high_cnt, >>>                    itr->t_low_cnt, itr->t_cycle_cnt); >>>   +    ret = geni_se_set_rate(&gi2c->se, 19200000); >> >> hard code ? > > Good point. The 19.2 MHz value is not intended to be a permanent > limitation. > > This matches the frequency currently used by the I2C driver and > therefore preserves > > the existing behavior. If support for higher source clock frequencies > (e.g. 32 MHz or others) > This is already added in driver for 32 MHz and also AFAIK, support is added for 3.4 MHZ which considers 100Mhz. so make it something which is generic. Hard code is not recommended here. Can we store source freq selection and continue with that ? > is added in the future, the requested OPP/performance state will need to > be updated accordingly. > > >> May work currently, but if higher frequency support added, source may >> change. >> >> Also you have added in commit message, but add a comment also here. >> [...]