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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43946bff4d4sm14580465e9.3.2025.02.10.00.40.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 00:40:33 -0800 (PST) Message-ID: <4f058421-e0de-4a81-9452-e19684132998@redhat.com> Date: Mon, 10 Feb 2025 09:40:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase To: Peter Maydell Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com, jasowang@redhat.com, imammedo@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, clg@redhat.com, philmd@linaro.org, zhenzhong.duan@intel.com, ddutile@redhat.com References: <20250206142307.921070-1-eric.auger@redhat.com> <20250206142307.921070-5-eric.auger@redhat.com> <7102d470-ac72-4c02-b8bc-20f1379a4843@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: etvnXDq3bWz6pHRZYTQTXdSJsj9AYmNDGyWMpwmeJrY_1739176834 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.405, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: CDLAmSlW3KXm Hi Peter, On 2/7/25 5:58 PM, Peter Maydell wrote: > On Fri, 7 Feb 2025 at 16:50, Eric Auger wrote: >> >> >> >> On 2/7/25 5:37 PM, Peter Maydell wrote: >>> On Thu, 6 Feb 2025 at 14:23, Eric Auger wrote: >>>> Currently the iommu may be reset before the devices >>>> it protects. For example this happens with virtio-scsi-pci. >>>> when system_reset is issued from qmp monitor, spurious >>>> "virtio: zero sized buffers are not allowed" warnings can >>>> be observed. >>>> >>>> Signed-off-by: Eric Auger >>>> --- >>>> hw/arm/smmuv3.c | 9 +++++---- >>>> hw/arm/trace-events | 1 + >>>> 2 files changed, 6 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >>>> index c0cf5df0f6..7522c32b24 100644 >>>> --- a/hw/arm/smmuv3.c >>>> +++ b/hw/arm/smmuv3.c >>>> @@ -1870,13 +1870,14 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev) >>>> } >>>> } >>>> >>>> -static void smmu_reset_hold(Object *obj, ResetType type) >>>> +static void smmu_reset_exit(Object *obj, ResetType type) >>>> { >>>> SMMUv3State *s = ARM_SMMUV3(obj); >>>> SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); >>>> >>>> - if (c->parent_phases.hold) { >>>> - c->parent_phases.hold(obj, type); >>>> + trace_smmu_reset_exit(); >>>> + if (c->parent_phases.exit) { >>>> + c->parent_phases.exit(obj, type); >>>> } >>> If we need to do something unexpected like reset >>> register values in the exit phase rather than the >>> hold phase, it's a good idea to have a comment explaining >>> why, to avoid somebody coming along afterwards and tidying >>> it up into the more usual arrangement. >> sure >>> If I understand correctly we need to keep the whole IOMMU >>> config intact until the exit phase? What's the thing the >>> device behind the IOMMU is trying to do during its reset >>> that triggers the warning? >> The virtio-pci-net continues to perform DMA requests and this causes >> some weird messages such as: >> "virtio: bogus descriptor or out of resources" >> >> Also VFIO devices may continue issuing DMAs causing translation faults > Hmm, right. I guess this only happens with KVM, or can you > trigger it in a TCG setup too? Anyway, presumably we can I have only tested with KVM acceleration for now. > rely on the devices quiescing all their outstanding DMA > by the time the hold phase comes along. > > (I wonder if we ought to suggest quiescing outstanding > DMA in the enter phase? But it's probably easier to fix > the iommus like this series does than try to get every > dma-capable pci device to do something different.) at least we can document this, as Peter later suggests. Indeed fixing it at vIOMMU level looked much easier for me, hoping that no other DMA capable device would stop DMAs at exit phase Eric > > thanks > -- PMM >