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[72.194.116.95]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a0b0d00b007426e664cdcsm3101839qkg.133.2023.04.17.05.59.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Apr 2023 05:59:24 -0700 (PDT) Message-ID: <4f09dad9-eb49-4a26-7237-79b1ec171486@gmail.com> Date: Mon, 17 Apr 2023 05:59:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH net-next 3/7] net: mscc: ocelot: optimize ocelot_mm_irq() Content-Language: en-US To: Vladimir Oltean , netdev@vger.kernel.org Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Claudiu Manoil , Alexandre Belloni , UNGLinuxDriver@microchip.com, Xiaoliang Yang , linux-kernel@vger.kernel.org References: <20230415170551.3939607-1-vladimir.oltean@nxp.com> <20230415170551.3939607-4-vladimir.oltean@nxp.com> From: Florian Fainelli In-Reply-To: <20230415170551.3939607-4-vladimir.oltean@nxp.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/15/2023 10:05 AM, Vladimir Oltean wrote: > The MAC Merge IRQ of all ports is shared with the PTP TX timestamp IRQ > of all ports, which means that currently, when a PTP TX timestamp is > generated, felix_irq_handler() also polls for the MAC Merge layer status > of all ports, looking for changes. This makes the kernel do more work, > and under certain circumstances may make ptp4l require a > tx_timestamp_timeout argument higher than before. > > Changes to the MAC Merge layer status are only to be expected under > certain conditions - its TX direction needs to be enabled - so we can > check early if that is the case, and omit register access otherwise. > > Make ocelot_mm_update_port_status() skip register access if > mm->tx_enabled is unset, and also call it once more, outside IRQ > context, from ocelot_port_set_mm(), when mm->tx_enabled transitions from > true to false, because an IRQ is also expected in that case. > > Also, a port may have its MAC Merge layer enabled but it may not have > generated the interrupt. In that case, there's no point in writing to > DEV_MM_STATUS to acknowledge that IRQ. We can reduce the number of > register writes per port with MM enabled by keeping an "ack" variable > which writes the "write-one-to-clear" bits. Those are 3 in number: > PRMPT_ACTIVE_STICKY, UNEXP_RX_PFRM_STICKY and UNEXP_TX_PFRM_STICKY. > The other fields in DEV_MM_STATUS are read-only and it doesn't matter > what is written to them, so writing zero is just fine. > > Signed-off-by: Vladimir Oltean Reviewed-by: Florian Fainelli -- Florian