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Mon, 24 Aug 2026 15:41:48 GMT Received: from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4g7q3jpvcw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Aug 2026 15:41:48 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (smtpav06.wdc07v.mail.ibm.com [10.39.53.233]) by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67OFfkwF22151890 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 24 Aug 2026 15:41:47 GMT Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2CEE5803F; Mon, 24 Aug 2026 15:41:46 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C11058055; Mon, 24 Aug 2026 15:41:45 +0000 (GMT) Received: from mambor8.rchland.ibm.com (unknown [9.10.239.198]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 24 Aug 2026 15:41:45 +0000 (GMT) Message-ID: <4fdbe85d9ce0610984be3c28a86077fee3b69d11.camel@linux.ibm.com> Subject: Re: [PATCH 28/29] target/ppc: Move byte-reverse instructions to decodetree From: Miles Glenn To: Chinmay Rath , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com Date: Mon, 24 Aug 2026 10:41:45 -0500 In-Reply-To: <20260820140114.327023-29-rathc@linux.ibm.com> References: <20260820140114.327023-1-rathc@linux.ibm.com> <20260820140114.327023-29-rathc@linux.ibm.com> Organization: IBM Content-Type: text/plain; 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envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles Thanks, Glenn On Thu, 2026-08-20 at 19:30 +0530, Chinmay Rath wrote: > From: Vishal Chourasia > > Moving the following instructions to decodetree specification: > brd, brw, brh : X-form > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the > `-d in_asm,op` flag. > > This also includes improvements from review feedback: > - Add TARGET_PPC64 guards with qemu_build_not_reached() for 32-bit builds > > Signed-off-by: Vishal Chourasia > Signed-off-by: Chinmay Rath > --- > target/ppc/insn32.decode | 5 +++ > target/ppc/translate.c | 35 ------------------- > target/ppc/translate/fixedpoint-impl.c.inc | 40 ++++++++++++++++++++++ > 3 files changed, 45 insertions(+), 35 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index f7ab08704f..7614655f72 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -320,6 +320,11 @@ MFMSR 011111 ..... ----- ----- 0001010011 - @X_t > MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l > MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l > > +### Fixed-Point Byte-Reverse Instructions > +BRW 011111 ..... ..... ----- 0010011011 - @X_sa > +BRD 011111 ..... ..... ----- 0010111011 - @X_sa > +BRH 011111 ..... ..... ----- 0011011011 - @X_sa > + > ### Fixed-Point Load Instructions > > LBZ 100010 ..... ..... ................ @D > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 9d29134fa1..8950476be7 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -4532,42 +4532,7 @@ static void gen_dform3D(DisasContext *ctx) > return gen_invalid(ctx); > } > > -#if defined(TARGET_PPC64) > -/* brd */ > -static void gen_brd(DisasContext *ctx) > -{ > - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > -} > - > -/* brw */ > -static void gen_brw(DisasContext *ctx) > -{ > - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > - tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); > - > -} > - > -/* brh */ > -static void gen_brh(DisasContext *ctx) > -{ > - TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); > - TCGv_i64 t1 = tcg_temp_new_i64(); > - TCGv_i64 t2 = tcg_temp_new_i64(); > - > - tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); > - tcg_gen_and_i64(t2, t1, mask); > - tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); > - tcg_gen_shli_i64(t1, t1, 8); > - tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); > -} > -#endif > - > static opcode_t opcodes[] = { > -#if defined(TARGET_PPC64) > -GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), > -GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), > -GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), > -#endif > GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), > GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), > GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > index a75279022c..cef67d6431 100644 > --- a/target/ppc/translate/fixedpoint-impl.c.inc > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -17,6 +17,46 @@ > * License along with this library; if not, see . > */ > > +/* > + * Byte-Reverse Instructions > + */ > +static bool do_byte_reverse_X_sa(DisasContext *ctx, arg_X_sa *a, int kind) > +{ > +#if defined(TARGET_PPC64) > + switch (kind) { > + case 0: /* brd */ > + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); > + break; > + case 1: /* brw */ > + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); > + tcg_gen_rotli_i64(cpu_gpr[a->ra], cpu_gpr[a->ra], 32); > + break; > + case 2: /* brh */ > + { > + TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + > + tcg_gen_shri_i64(t1, cpu_gpr[a->rs], 8); > + tcg_gen_and_i64(t2, t1, mask); > + tcg_gen_and_i64(t1, cpu_gpr[a->rs], mask); > + tcg_gen_shli_i64(t1, t1, 8); > + tcg_gen_or_i64(cpu_gpr[a->ra], t1, t2); > + break; > + } > + default: > + g_assert_not_reached(); > + } > +#else > + qemu_build_not_reached(); > +#endif > + return true; > +} > + > +TRANS64_FLAGS2(ISA310, BRD, do_byte_reverse_X_sa, 0) > +TRANS64_FLAGS2(ISA310, BRW, do_byte_reverse_X_sa, 1) > +TRANS64_FLAGS2(ISA310, BRH, do_byte_reverse_X_sa, 2) > + > /* > * Fixed-Point Load/Store Instructions > */