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Tsirkin" , =?UTF-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org References: <20250620092734.1576677-1-zhao1.liu@intel.com> <20250620092734.1576677-2-zhao1.liu@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20250620092734.1576677-2-zhao1.liu@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 6/20/2025 5:27 PM, Zhao Liu wrote: > Refer to SDM vol.3 table 1-21, add the notes about the missing > descriptor, and fix the typo and comment format. > > Signed-off-by: Zhao Liu > --- > target/i386/cpu.c | 31 ++++++++++++++++++++++--------- > 1 file changed, 22 insertions(+), 9 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 40aefb38f6da..e398868a3f8d 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -66,6 +66,7 @@ struct CPUID2CacheDescriptorInfo { > > /* > * Known CPUID 2 cache descriptors. > + * TLB, prefetch and sectored cache related descriptors are not included. > * From Intel SDM Volume 2A, CPUID instruction > */ > struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { > @@ -87,18 +88,29 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { > .associativity = 2, .line_size = 64, }, > [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, > .associativity = 8, .line_size = 64, }, > - /* lines per sector is not supported cpuid2_cache_descriptor(), > - * so descriptors 0x22, 0x23 are not included > - */ > + /* > + * lines per sector is not supported cpuid2_cache_descriptor(), > + * so descriptors 0x22, 0x23 are not included > + */ > [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, > .associativity = 16, .line_size = 64, }, > - /* lines per sector is not supported cpuid2_cache_descriptor(), > - * so descriptors 0x25, 0x20 are not included > - */ > + /* > + * lines per sector is not supported cpuid2_cache_descriptor(), > + * so descriptors 0x25, 0x29 are not included > + */ > [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, > .associativity = 8, .line_size = 64, }, > [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, > .associativity = 8, .line_size = 64, }, > + /* > + * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL) > + * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2 > + * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid > + * to just ignore l3's code if there's no l3. s/l3/L3/g Others look good to me.  Reviewed-by: Dapeng Mi > + * > + * This already covers all the cases in QEMU, so code 0x40 is not > + * included. > + */ > [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, > .associativity = 4, .line_size = 32, }, > [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, > @@ -136,9 +148,10 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { > .associativity = 4, .line_size = 64, }, > [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, > .associativity = 4, .line_size = 64, }, > - /* lines per sector is not supported cpuid2_cache_descriptor(), > - * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. > - */ > + /* > + * lines per sector is not supported cpuid2_cache_descriptor(), > + * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. > + */ > [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, > .associativity = 8, .line_size = 64, }, > [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,