From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sr7JB-0001X0-11 for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:55:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sr7J6-0007ia-LB for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:55:20 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:37155) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sr7J6-0007hh-FI for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:55:16 -0400 Received: from eusync4.samsung.com (mailout4.w1.samsung.com [210.118.77.14]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7B00C442KYKY80@mailout4.w1.samsung.com> for qemu-devel@nongnu.org; Tue, 17 Jul 2012 13:55:46 +0100 (BST) Received: from [106.109.9.94] by eusync4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7B00JTB2JQGS00@eusync4.samsung.com> for qemu-devel@nongnu.org; Tue, 17 Jul 2012 13:55:07 +0100 (BST) Message-id: <500560A6.9000500@samsung.com> Date: Tue, 17 Jul 2012 16:55:02 +0400 From: Igor Mitsyanko MIME-version: 1.0 References: <0020234e7fc3001f66ef67a1d3e19a01b6e498a5.1341457220.git.peter.crosthwaite@petalogix.com> In-reply-to: Content-type: text/plain; charset=UTF-8; format=flowed Content-transfer-encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 2/4] exynos4210: Added SD host controller model List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: e.voevodin@samsung.com, qemu-devel@nongnu.org, "Peter A. G. Crosthwaite" , kyungmin.park@samsung.com, d.solodkiy@samsung.com, edgar.iglesias@gmail.com, m.kozlov@samsung.com, john.williams@petalogix.com On 07/16/2012 09:13 PM, Peter Maydell wrote: > On 5 July 2012 05:04, Peter A. G. Crosthwaite > wrote: >> From: Igor Mitsyanko >> >> Custom Exynos4210 SD/MMC host controller, based on SD association standard host >> controller ver. 2.00. >> >> Signed-off-by: Igor Mitsyanko >> --- >> changed from v4 (Igor): >> set irq on SLOTINT status instead of interrupt registers status; instead; > The IRQ handling code still looks really weird. I would expect > that the code would be: > [code which updates various kinds of irq related state] > sdhci_update_irq(); > > where sdhci_update_irq() calls qemu_set_irq() based on the state. > > At the moment it looks as if you're using slotint as a cached value > of the expression > "((s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || > ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || > ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)))" > > [can these two ever have different values?] and also attempting to > shortcut by manually updating slotint in codepaths which change only > parts of the state which this expression is testing. Why not just do > things the simple and straightforward way and get rid of slotint > completely? > > -- PMM > Linux seems to ignore SLOTINT status register, probably because it only supports single slot configuration while SLOTINT really required for multislot controllers only, so I think we can remove it completely and simply return 0 on reads. Same for status of WAKCON register, nobody cares about controller's wakeup functionality. Then update irq function could be simplified to "qemu_set_irq(s->irq, (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen))" I think thats how it was done originally. I'll send incremental patch to Peter off-list, if he and everyone else agree to handle interrupts this way.