From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1StGP3-0006OO-0j for qemu-devel@nongnu.org; Mon, 23 Jul 2012 07:02:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1StGOs-0003bs-6m for qemu-devel@nongnu.org; Mon, 23 Jul 2012 07:02:16 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:25314) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1StGOs-0003bU-0N for qemu-devel@nongnu.org; Mon, 23 Jul 2012 07:02:06 -0400 Received: from eusync1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7M00C8L1C7JH40@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Mon, 23 Jul 2012 12:02:31 +0100 (BST) Received: from [106.109.9.187] by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0M7M003QG1AZ2S30@eusync1.samsung.com> for qemu-devel@nongnu.org; Mon, 23 Jul 2012 12:02:03 +0100 (BST) Date: Mon, 23 Jul 2012 15:01:42 +0400 From: Maksim Kozlov In-reply-to: Message-id: <500D2F16.5000209@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8; format=flowed Content-transfer-encoding: QUOTED-PRINTABLE References: <1342112068-23345-1-git-send-email-m.kozlov@samsung.com> <1342112068-23345-5-git-send-email-m.kozlov@samsung.com> Subject: Re: [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: kyungmin.park@samsung.com, qemu-devel@nongnu.org, e.voevodin@samsung.com 20.07.2012 18:32, Peter Maydell =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > On 12 July 2012 17:54, Maksim Kozlov wrote: >> Signed-off-by: Maksim Kozlov >> --- >> hw/exynos4210_pmu.c | 40 +++++++++++++++++++++++++++++++++----= --- >> 1 files changed, 33 insertions(+), 7 deletions(-) >> >> diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c >> index 7f09c79..96588d9 100644 >> --- a/hw/exynos4210_pmu.c >> +++ b/hw/exynos4210_pmu.c >> @@ -18,13 +18,8 @@ >> * with this program; if not, see= . >> */ >> >> -/* >> - * This model implements PMU registers just as a bulk of memory. = Currently, >> - * the only reason this device exists is that secondary CPU boot = loader >> - * uses PMU INFORM5 register as a holding pen. >> - */ >> - >> #include "sysbus.h" >> +#include "sysemu.h" >> >> #ifndef DEBUG_PMU >> #define DEBUG_PMU 0 >> @@ -230,6 +225,8 @@ >> >> #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c >> >> +#define SWRESET_SYSTEM_MASK 0x00000001 >> + >> typedef struct Exynos4210PmuReg { >> const char *name; /* for debug only */ >> uint32_t offset; >> @@ -458,7 +455,17 @@ static void exynos4210_pmu_write(void *opaque= , target_phys_addr_t offset, >> PRINT_DEBUG_EXTEND("%s [0x%04x]<- 0x%04x\n", >> exynos4210_pmu_regs[index].name, (uint32_t)offset, = (uint32_t)val); >> >> - s->reg[index] =3D val; >> + switch (offset) { >> + case SWRESET: >> + if (val& SWRESET_SYSTEM_MASK) { >> + s->reg[index] =3D val; >> + qemu_system_reset_request(); >> + } >> + break; >> + default: >> + s->reg[index] =3D val; >> + break; >> + } >> } >> >> static const MemoryRegionOps exynos4210_pmu_ops =3D { >> @@ -477,9 +484,28 @@ static void exynos4210_pmu_reset(DeviceState = *dev) >> Exynos4210PmuState *s =3D >> container_of(dev, Exynos4210PmuState, busdev.qdev); >> unsigned i; >> + uint32_t index =3D exynos4210_pmu_get_register_index(s, SWRES= ET); >> + uint32_t swreset =3D s->reg[index]; >> >> /* Set default values for registers */ >> for (i =3D 0; i< PMU_NUM_OF_REGISTERS; i++) { >> + if (swreset) { >> + switch (exynos4210_pmu_regs[i].offset) { >> + case INFORM0: >> + case INFORM1: >> + case INFORM2: >> + case INFORM3: >> + case INFORM4: >> + case INFORM5: >> + case INFORM6: >> + case INFORM7: >> + case PS_HOLD_CONTROL: >> + /* keep these registers during SW reset */ >> + continue; >> + default: >> + break; >> + } >> + } >> s->reg[i] =3D exynos4210_pmu_regs[i].reset_value; >> } >> } > This patch seems to be trying to make a distinction that QEMU doesn= 't > support, ie between system wide "software reset" and system wide > "hard reset". I'm not convinced about the wisdom of trying to paper > over this lack with a single-device workaround. Peter, if we add callback (*swreset)() into DeviceClass, whether it w= ill=20 be an acceptable solution? And devices which have different behavior= =20 during swreset can register different function for that. What do you= =20 think about this? > > -- PMM > --=20 Best regards, Maksim Kozlov Leading Engineer Advanced Software Group, Samsung Moscow Research Center e-mail: m.kozlov@samsung.com Tel: 7(495) 797-25-00 ext. 3949