diff for duplicates of <5010451.G368NqnOYK@phil> diff --git a/a/1.txt b/N1/1.txt index d8217bd..19ec904 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -32,7 +32,7 @@ the patch. > }; > }; > -> + i2s0: i2s at 10118000 { +> + i2s0: i2s@10118000 { > + compatible = "rockchip,rk3066-i2s"; > + reg = <0x10118000 0x2000>; > + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; @@ -47,7 +47,7 @@ the patch. > + status = "disabled"; > + }; > + -> + i2s1: i2s at 1011a000 { +> + i2s1: i2s@1011a000 { > + compatible = "rockchip,rk3066-i2s"; > + reg = <0x1011a000 0x2000>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; @@ -62,7 +62,7 @@ the patch. > + status = "disabled"; > + }; > + -> + i2s2: i2s at 1011c000 { +> + i2s2: i2s@1011c000 { > + compatible = "rockchip,rk3066-i2s"; > + reg = <0x1011c000 0x2000>; > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -77,7 +77,7 @@ the patch. > + status = "disabled"; > + }; > + -> cru: clock-controller at 20000000 { +> cru: clock-controller@20000000 { > compatible = "rockchip,rk3066a-cru"; > reg = <0x20000000 0x1000>; > @@ -405,6 +450,42 @@ @@ -131,7 +131,7 @@ the patch. > }; > }; > -> + i2s0: i2s at 1011a000 { +> + i2s0: i2s@1011a000 { > + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; > + reg = <0x1011a000 0x2000>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; @@ -146,7 +146,7 @@ the patch. > + status = "disabled"; > + }; > + -> cru: clock-controller at 20000000 { +> cru: clock-controller@20000000 { > compatible = "rockchip,rk3188-cru"; > reg = <0x20000000 0x1000>; > @@ -395,6 +410,17 @@ diff --git a/a/content_digest b/N1/content_digest index e1c6ccd..cbd1857 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,18 @@ "ref\01413274597-15788-1-git-send-email-julien.chauveau@neo-technologies.fr\0" - "From\0heiko@sntech.de (Heiko St\303\274bner)\0" - "Subject\0[PATCH v2] ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188\0" + "From\0Heiko St\303\274bner <heiko@sntech.de>\0" + "Subject\0Re: [PATCH v2] ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188\0" "Date\0Wed, 15 Oct 2014 16:07:55 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>\0" + "Cc\0Rob Herring <robh+dt@kernel.org>" + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + Russell King <linux@arm.linux.org.uk> + moderated list:ARM/Rockchip SoC... <linux-arm-kernel@lists.infradead.org> + open list:ARM/Rockchip SoC... <linux-rockchip@lists.infradead.org> + open list:OPEN FIRMWARE AND... <devicetree@vger.kernel.org> + " open list <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "Hi Julien,\n" @@ -39,7 +49,7 @@ "> \t\t};\n" "> \t};\n" "> \n" - "> +\ti2s0: i2s at 10118000 {\n" + "> +\ti2s0: i2s@10118000 {\n" "> +\t\tcompatible = \"rockchip,rk3066-i2s\";\n" "> +\t\treg = <0x10118000 0x2000>;\n" "> +\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -54,7 +64,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\ti2s1: i2s at 1011a000 {\n" + "> +\ti2s1: i2s@1011a000 {\n" "> +\t\tcompatible = \"rockchip,rk3066-i2s\";\n" "> +\t\treg = <0x1011a000 0x2000>;\n" "> +\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -69,7 +79,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\ti2s2: i2s at 1011c000 {\n" + "> +\ti2s2: i2s@1011c000 {\n" "> +\t\tcompatible = \"rockchip,rk3066-i2s\";\n" "> +\t\treg = <0x1011c000 0x2000>;\n" "> +\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -84,7 +94,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> \tcru: clock-controller at 20000000 {\n" + "> \tcru: clock-controller@20000000 {\n" "> \t\tcompatible = \"rockchip,rk3066a-cru\";\n" "> \t\treg = <0x20000000 0x1000>;\n" "> @@ -405,6 +450,42 @@\n" @@ -138,7 +148,7 @@ "> \t\t};\n" "> \t};\n" "> \n" - "> +\ti2s0: i2s at 1011a000 {\n" + "> +\ti2s0: i2s@1011a000 {\n" "> +\t\tcompatible = \"rockchip,rk3188-i2s\", \"rockchip,rk3066-i2s\";\n" "> +\t\treg = <0x1011a000 0x2000>;\n" "> +\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -153,7 +163,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> \tcru: clock-controller at 20000000 {\n" + "> \tcru: clock-controller@20000000 {\n" "> \t\tcompatible = \"rockchip,rk3188-cru\";\n" "> \t\treg = <0x20000000 0x1000>;\n" "> @@ -395,6 +410,17 @@\n" @@ -174,4 +184,4 @@ "> \t};\n" > }; -db5e5c10f443fcc88c671f49ede64b8cfd0d6100f32511c306878e11fb5f531c +851775da269e189f67f35ed6d21d874c328fd702ee5246b99a1118d7442c2edf
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