From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH 2 of 5] (V2) rombios/ata: Do not wait for
 BSY to be set
Date: Tue, 31 Jul 2012 10:37:16 +0100
Message-ID: <5017A74C.6090006@citrix.com>
References: <patchbomb.1343677639@andrewcoop.uk.xensource.com>
	<59de21ca15462034c147.1343677641@andrewcoop.uk.xensource.com>
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Cc: "Keir (Xen.org)" <keir@xen.org>, Jan Beulich <jbeulich@suse.com>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
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On 30/07/12 21:18, Pasi Kärkkäinen wrote:
> On Mon, Jul 30, 2012 at 08:47:21PM +0100, Andrew Cooper wrote:
>> I can't find any guarantee in the ATA specification that this will happen, and it
>> certainly does not with Qemu.  SeaBIOS has replaced it with a call to udelay(5)
>> instead.
>>
>> As rombios does not have an equivalent udelay(), so replace the wait with a write
>> to port 0x80 which is whilelisted by Xen for 'a small delay'.
>>                          ^
> a small typo probably.. I think it should say "whitelisted".
>
> -- Pasi
>
 D'oh - yes.  Attached is version 2 which corrects this, and another
grammatical error in the sentence.

-- 
Andrew Cooper - Dom0 Kernel Engineer, Citrix XenServer
T: +44 (0)1223 225 900, http://www.citrix.com


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# HG changeset patch
# Parent 2c92985dc53fbc62d1a2975aed968a8bb021c8ef
rombios/ata: Do not wait for BSY to be set

I can't find any guarantee in the ATA specification that this will happen, and it
certainly does not with Qemu.  SeaBIOS has replaced it with a call to udelay(5)
instead.

As rombios does not have an equivalent udelay(), replace the wait with a write
to port 0x80 which is whitelisted by Xen for 'a small delay'.

This causes roughly 42k fewer traps to Qemu, which is very roughly 10% of the
number of traps during boot of a Win7 guest.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff -r 2c92985dc53f tools/firmware/rombios/rombios.c
--- a/tools/firmware/rombios/rombios.c
+++ b/tools/firmware/rombios/rombios.c
@@ -2914,8 +2914,8 @@ Bit16u device;
 // 8.2.1 (a) -- set SRST in DC
   outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN | ATA_CB_DC_SRST);
 
-// 8.2.1 (b) -- wait for BSY
-  await_ide(BSY, iobase1, 20);
+// 8.2.1 (b) -- wait
+  outb(0x80, 0x00);
 
 // 8.2.1 (f) -- clear SRST
   outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN);

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