From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xiao Guangrong Subject: Re: [PATCH 02/10] nEPT: Add EPT tables support to paging_tmpl.h Date: Fri, 03 Aug 2012 16:08:21 +0800 Message-ID: <501B86F5.9030209@linux.vnet.ibm.com> References: <1343831766-nyh@il.ibm.com> <201208011437.q71Ebfif023819@rice.haifa.ibm.com> <5019FB79.40407@linux.vnet.ibm.com> <20120802212533.GA11601@fermat.math.technion.ac.il> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Cc: kvm@vger.kernel.org, Joerg.Roedel@amd.com, avi@redhat.com, owasserm@redhat.com, abelg@il.ibm.com, eddie.dong@intel.com, yang.z.zhang@intel.com To: "Nadav Har'El" Return-path: Received: from e28smtp05.in.ibm.com ([122.248.162.5]:39984 "EHLO e28smtp05.in.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751689Ab2HCIIb (ORCPT ); Fri, 3 Aug 2012 04:08:31 -0400 Received: from /spool/local by e28smtp05.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 3 Aug 2012 13:38:28 +0530 Received: from d28av04.in.ibm.com (d28av04.in.ibm.com [9.184.220.66]) by d28relay03.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q7388Pwi22479058 for ; Fri, 3 Aug 2012 13:38:25 +0530 Received: from d28av04.in.ibm.com (loopback [127.0.0.1]) by d28av04.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q7388Ofh014665 for ; Fri, 3 Aug 2012 18:08:25 +1000 In-Reply-To: <20120802212533.GA11601@fermat.math.technion.ac.il> Sender: kvm-owner@vger.kernel.org List-ID: On 08/03/2012 05:25 AM, Nadav Har'El wrote: > On Thu, Aug 02, 2012, Xiao Guangrong wrote about "Re: [PATCH 02/10] nEPT: Add EPT tables support to paging_tmpl.h": >>> + #ifdef CONFIG_X86_64 >>> + #define PT_MAX_FULL_LEVELS 4 >>> + #define CMPXCHG cmpxchg >>> + #else >>> + #define CMPXCHG cmpxchg64 >>> + #define PT_MAX_FULL_LEVELS 2 >>> + #endif >> >> Missing the case of FULL_LEVELS == 3? Oh, you mentioned it >> as PAE case in the PATCH 0. > > I understood this differently (and it would not be surprising if > wrongly...): With nested EPT, we only deal with two *EPT* tables - > the shadowed page table and shadow page table are both EPT. > And EPT tables cannot have three levels - even if PAE is used. Or at least, > that's what I thought... > >> Note A/D bits are supported on new intel cpus, this function should be reworked >> for nept. I know you did not export this feather to guest, but we can reduce >> the difference between nept and other mmu models if A/D are supported. > > I'm not sure what you meant: If the access/dirty bits are supported in > newer cpus, do you think we *should* support them also in the processor > L1 processor, or are you saying that it would be easier to support them > because this is what the shadow page table code normally does anyway, > so *not* supporting them will take effort? I mean "it would be easier to support them because this is what the shadow page table code normally does anyway, so *not* supporting them will take effort" :) Then, we can drop "ifndef PTTYPT_EPT"... Actuality, we can redefine some bits (like PRSENT, WRTIABLE, DRITY...) to let the paging_tmpl code work for all models. > >>> +#if PTTYPE != PTTYPE_EPT >>> static int FNAME(walk_addr_nested)(struct guest_walker *walker, >>> struct kvm_vcpu *vcpu, gva_t addr, >>> u32 access) >>> @@ -335,6 +395,7 @@ static int FNAME(walk_addr_nested)(struc >>> return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, >>> addr, access); >>> } >>> +#endif >>> >> >> Hmm, you do not need the special walking functions? > > Since these functions are static, the compiler warns me on every > function that is never used, so I had to #if them out... > > IIUC, you did not implement the functions (like walk_addr_nested) to translate L2's VA to L2's PA, yes? (it is needed for emulation.)