From: Scott Wood <scottwood@freescale.com>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>,
Varun Sethi <Varun.Sethi@freescale.com>,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error interrupt support.
Date: Fri, 3 Aug 2012 11:44:55 -0500 [thread overview]
Message-ID: <501C0007.8070209@freescale.com> (raw)
In-Reply-To: <609EA81E-EC64-4539-B36B-E57525CE2492@kernel.crashing.org>
On 08/03/2012 08:19 AM, Kumar Gala wrote:
>
> On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
>> + /* ioremap'ed base for error interrupt registers */
>> + u32 __iomem *err_regs;
>> + /* error interrupt config */
>> + u32 err_int_config_done;
>> +
>
> Is this really needed ?
Probably a left over from when it was done on demand.
>
>> /* Protected sources */
>> unsigned long *protected;
>>
>> @@ -370,6 +381,8 @@ struct mpic
>> #define MPIC_NO_RESET 0x00004000
>> /* Freescale MPIC (compatible includes "fsl,mpic") */
>> #define MPIC_FSL 0x00008000
>> +/* Freescale MPIC supports EIMR (error interrupt mask register)*/
>> +#define MPIC_FSL_HAS_EIMR 0x00010000
>
> Can't we use BRR for this?
BRR is used, and this is set as a result. Better than opencoding a BRR
check a bunch of places...
-Scott
next prev parent reply other threads:[~2012-08-03 16:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-31 14:42 [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error interrupt support Varun Sethi
2012-08-03 13:19 ` Kumar Gala
2012-08-03 16:44 ` Scott Wood [this message]
2012-08-03 19:13 ` Kumar Gala
2012-08-03 19:16 ` Sethi Varun-B16395
2012-08-03 19:21 ` Kumar Gala
2012-08-03 18:52 ` Sethi Varun-B16395
2012-08-03 19:24 ` Kumar Gala
2012-08-03 19:32 ` Sethi Varun-B16395
2012-08-07 18:57 ` Scott Wood
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