From: Peter Barada <peter.barada@logicpd.com>
To: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
Peter Barada <peter.barada@logicpd.com>
Subject: OMAP34xx HW 1-bit ECC algorithm
Date: Tue, 14 Aug 2012 12:59:54 -0400 [thread overview]
Message-ID: <502A840A.4000106@logicpd.com> (raw)
Is there any source for code that generates a 3-byte subpage ECC that
matches the ECC the bootrom is expecting when reading bootloader code
out of the first block of NAND?
I'm dealing with a problem of the Micron MT46H256M32L4K1-5 that has a
in-chip BCH ECC engine on our boards where a reset doesn't clear the
in-chip ECC. The in-chip ECC resides at bytes 8-15, 24-31, 40-47, 56-63
of the OOB, and the first half-page ECC overlaps the 3rd and 4th page HW
1-bit ECC. I need to synthesize data in the 3rd/4th subpages for the
code loaded from the bootloader that matches bytes 8-12 of the Micron
in-chip ECC.
Thanks in advance!
--
Peter Barada
peter.barada@logicpd.com
reply other threads:[~2012-08-14 17:04 UTC|newest]
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